XR72L52 Datasheet, PDF (15/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L52
REV. 1.0.1
Figure 160. The Terminal Equipment being interfaced to the Transmit Overhead Data Input Interface (Method 2)..... 374
TABLE 72: THE RELATIONSHIP BETWEEN THE NUMBER OF TXOHENABLE PULSES (SINCE THE LAST OCCURRENCE OF THE
TXOHFRAME PULSE) TO THE E3 OVERHEAD BIT, THAT IS BEING PROCESSED BY THE XRT72L52 ...................... 374
Figure 161. Behavior of Transmit Overhead Data Input Interface signals between the XRT72L52 and the Terminal
Equipment (for Method 2).............................................................................................................................. 377
6.2.3 The Transmit E3 HDLC Controller ....................................................................................................... 377
Figure 162. LAPD Message Frame Format.................................................................................................................. 378
TABLE 73: THE LAPD MESSAGE TYPE AND THE CORRESPONDING VALUE OF THE FIRST BYTE, WITHIN THE INFORMATION PAYLOAD
379
TRANSMIT E3 LAPD CONFIGURATION REGISTER (ADDRESS = 0X33) ....................................................... 380
TABLE 74: RELATIONSHIP BETWEEN TXLAPD MSG LENGTH AND THE LAPD MESSAGE SIZE ............................................. 380
TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30) .............................................................................. 380
TXE3 LAPD CONFIGURATION REGISTER (ADDRESS = 0X33) ................................................................... 381
TRANSMIT E3 LAPD CONFIGURATION REGISTER (ADDRESS = 0X33) ....................................................... 381
TXE3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34)........................................................ 382
TXE3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34)........................................................ 382
Figure 163. Flow Chart depicting how to use the LAPD Transmitter (LAPD Transmitter is configured to re-transmit the LAPD
Message frame repeatedly at One-Second intervals) ................................................................................... 384
Figure 164. Flow Chart depicting how to use the LAPD Transmitter (LAPD Transmitter is configured to transmit a LAPD
Message frame only once). ........................................................................................................................... 385
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04) ....................................................................... 386
6.2.4 The Transmit E3 Framer Block ............................................................................................................ 386
Figure 165. The Transmit E3 Framer Block and the associated paths to other Functional Blocks............................... 387
TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30) .............................................................................. 388
TABLE 75: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TX AIS ENABLE) WITHIN THE TX E3 CONFIGURATION REGISTER,
AND THE RESULTING TRANSMIT E3 FRAMER BLOCK'S ACTION ........................................................................... 388
TABLE 76: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (TX LOS) WITHIN THE TX E3 CONFIGURATION REGISTER, AND
THE RESULTING TRANSMIT E3 FRAMER BLOCK'S ACTION .................................................................................. 389
6.2.5 The Transmit E3 Line Interface Block .................................................................................................. 390
Figure 166. Interfacing the XRT72L52 Framer IC to the XRT73L00 DS3/E3/STS-1 LIU ............................................. 391
Figure 167. The Transmit E3 LIU Interface block ......................................................................................................... 392
Figure 168. The Behavior of TxPOS and TxNEG signals during data transmission while the Transmit E3 LIU Interface is
operating in the Unipolar Mode ..................................................................................................................... 392
I/O CONTROL REGISTER (ADDRESS = 0X01)............................................................................................ 393
TABLE 77: THE RELATIONSHIP BETWEEN THE CONTENT OF BIT 3 (UNIPOLAR/BIPOLAR) WITHIN THE UNI I/O CONTROL REGISTER
AND THE TRANSMIT E3 FRAMER LINE INTERFACE OUTPUT MODE ...................................................................... 393
Figure 169. Illustration of AMI Line Code ..................................................................................................................... 394
Figure 170. Illustration of two examples of HDB3 Encoding......................................................................................... 394
I/O CONTROL REGISTER (ADDRESS = 0X01)............................................................................................ 395
TABLE 78: THE RELATIONSHIP BETWEEN BIT 4 (AMI/HDB3*) WITHIN THE I/O CONTROL REGISTER AND THE BIPOLAR LINE CODE
THAT IS OUTPUT BY THE TRANSMIT E3 LIU INTERFACE BLOCK .......................................................................... 395
TABLE 79: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TXLINECLK INV) WITHIN THE I/O CONTROL REGISTER AND THE
TXLINECLK CLOCK EDGE THAT TXPOS AND TXNEG ARE UPDATED ON ............................................................. 395
Figure 171. Waveform/Timing Relationship between TxLineClk, TxPOS and TxNEG - TxPOS and TxNEG are configured to
be updated on the rising edge of TxLineClk .................................................................................................. 396
Figure 172. Waveform/Timing Relationship between TxLineClk, TxPOS and TxNEG - TxPOS and TxNEG are configured to
be updated on the falling edge of TxLineClk ................................................................................................. 396
6.2.6 Transmit Section Interrupt Processing ................................................................................................. 396
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04) ....................................................................... 397
TXE3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34)........................................................ 397
TXE3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34)........................................................ 398
6.3 THE RECEIVE SECTION OF THE XRT72L52 (E3 MODE OPERATION) ................................................................. 398
Figure 173. The XRT72L52 Receive Section configured to operate in the E3 Mode ................................................... 399
6.3.1 The Receive E3 LIU Interface Block .................................................................................................... 399
Figure 174. The Receive E3 LIU Interface Block.......................................................................................................... 399
Figure 175. Behavior of the RxPOS, RxNEG and RxLineClk signals during data reception of Unipolar Data ............. 400
I/O CONTROL REGISTER (ADDRESS = 0X01)............................................................................................ 400
TABLE 80: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 3 (UNIPOLAR/BIPOLAR) WITHIN THE I/O CONTROL REGISTER400
Figure 176. Interfacing the XRT72L52 Framer IC to the XRT73L00 DS3/E3/STS-1 LIU ............................................. 401
Figure 177. Illustration of AMI Line Code ..................................................................................................................... 402
Figure 178. Illustration of two examples of HDB3 Decoding ........................................................................................ 402
I/O CONTROL REGISTER (ADDRESS = 0X01)............................................................................................ 403
TABLE 81: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (RXLINECLK INV) OF THE I/O CONTROL REGISTER, AND THE
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