XR72L52 Datasheet, PDF (100/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
This Read-Only bit-field reflects the state of the N-Bit-field, within the most recently received E3 frame.
2.3.5 Transmit DS3 Configuration Registers
2.3.5.1 Transmit DS3 Configuration Register
TRANSMIT DS3 CONFIGURATION REGISTER (ADDRESS = 0X30)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Tx Yellow
Alarm
Tx X Bits
Tx Idle
Tx AIS
Tx LOS
FERF on
LOS
FERF on
OOF
FERF on
AIS
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
1
1
1
Bit 7 - Tx Yellow Alarm
This Read/Write bit-field permits the user to command the Transmit DS3/E3 Framer block to transmit a Yellow
Alarm (e.g., X bits are all "0") in the outbound DS3 data stream.
Writing a "0" to this bit-field disables this feature (the default condition). In this condition, the X-bits in the out-
bound DS3 frame, are internally generated (based upon receiver conditions).
Writing a "1" to this bit-field invokes this command. In this condition, the Transmit DS3/E3 Framer block will
override the internally-generated X-bits and force all of the X-bits of each outbound DS3 frame to "0".
NOTES:
1. For more information in this feature, refer to Section 4.2.4.2.1.1.
2. This bit-setting is ignored if Bits 3, 4 or 5 (within this register) are set to "1".
Bit 6 - Tx X-Bit (Force X bits to "1")
This "Read/Write" bit-field permits the user to command the Transmit DS3/E3 Framer block to force all of the
X-bits, in the outbound DS3 Frames, to "1".
Writing a "0" to this bit-field disables this feature (the default condition). In this case, the Transmit DS3/E3
Framer block will generate X-bits based upon the receive conditions.
Writing a "1" to this bit-field invokes this command. In this case, the Transmit DS3/E3 Framer block will over-
write the internally-generated X-bits and set them all to "1".
NOTES:
1. For more information on this feature, refer to Section 4.2.4.2.1.2.
2. This bit-setting is ignored if Bits 3, 4, 5, or 7 (within this register) are set to "1".
Bit 5 - Tx Idle (Pattern)
This Read/Write bit-field permits the user to command the Transmit DS3/E3 Framer block to transmit the Idle
Condition pattern. If the user invokes this command, then the Transmit DS3/E3 Framer block will force the
outbound DS3 Frames to have the following patterns.
• Valid M-bits, F-bits and P-bits
• The three CP-Bits (F-frame #3) are "0"
• The X-bits are set to "1"
• A repeating "1100..." pattern in written into the payload portion of the DS3 Frames.
Writing a "1" to this bit-field invokes this command. Writing a "0" allows the Transmit DS3/E3 Framer block to
function normally (e.g., the Transmit DS3/E3 Framer block will transmit its payload and internally generated
overhead bits).
NOTE: For more information on this feature, refer to Section 4.2.4.2.1.3.
NOTE: This bit-setting is ignored if Bits 3 or 4 (within this register) are set to "1".
Bit 4 - Tx AIS (Pattern)
84