XR72L52 Datasheet, PDF (249/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L52
REV. 1.0.1
Servicing the Change of State on Receive Idle Interrupt
Whenever the XRT72L52 Framer IC detects this interrupt, it will do all of the following.
• It will assert the Interrupt Request Output pin (Int) by driving it "Low".
• It will set Bit 4 (Idle Interrupt Status), within the Rx DS3 Interrupt Status Register to “1”, as indicated below.
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13)
BIT 7
CP-Bit Error
Interrupt
Status
RUR
0
BIT 6
LOS
Interrupt
Status
RUR
0
BIT 5
AIS
Interrupt
Status
RUR
0
BIT 4
Idle Interrupt
Status
RUR
1
BIT 3
FERF
Interrupt
Status
RUR
0
BIT 2
AIC
Interrupt
Status
RUR
0
BIT 1
OOF
Interrupt
Status
RUR
0
BIT 0
P-Bit Error
Interrupt
Status
RUR
0
Whenever the Terminal Equipment encounters the Change in Idle Condition Receive Interrupt, it should do the
following.
1. It should determine the current state of the Idle condition. Recall, that this interrupt can generated, when-
ever the XRT72L52 Framer declares or clears the Idle condition. Hence, the current state of the Idle con-
dition can be determined by reading the state of Bit 5 (RxIdle), within the RxDS3 Configuration & Status
Registers, as illustrated below
RXDS3 CONFIGURATION & STATUS REGISTER (ADDRESS = 0X10)
BIT 7
RxAIS
RO
0
BIT 6
RxLOS
RO
0
BIT 5
RxIdle
RO
0
BIT 4
RxOOF
RO
0
BIT 3
Reserved
RO
X
BIT 2
Framing On
Parity
R/W
0
BIT 1
FSync
Algo
R/W
0
BIT 0
MSync
Algo
R/W
0
4.3.6.2.5 The Change of State of Receive FERF Interrupt
If the Change of State on Receive FERF Interrupt is enabled, then the XRT72L52 Framer IC will generate an
interrupt in response to either of the following conditions.
1. When the XRT72L52 Framer IC detects the FERF indicator, in the incoming DS3 data stream, and
2. When the XRT72L52 Framer IC no longer detects the FERF indicator, in the incoming DS3 data stream.
Conditions causing the XRT72L52 Framer IC to declare an FERF (Far-End-Receive Failure) condition
• If the Receive DS3 Framer block (within the XRT72L52 Framer IC) detects some incoming DS3 frames with
both of the X bits set to “0”.
Conditions causing the XRT72L52 Framer IC to clear the FERF condition.
• Whenever, the Receive DS3 Framer block starts to detect some incoming DS3 frames, in which the X bits
are not set to “0”.
Enabling and Disabling the Change of State on Receive FERF Interrupt:
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