XR72L52 Datasheet, PDF (6/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
FRAME PARITY ERRORS - ONE-SECOND ACCUMULATOR REGISTER - LSB (ADDRESS = 0X71)...................111
FRAME CP-BIT ERRORS - ONE-SECOND ACCUMULATOR REGISTER - MSB (ADDRESS = 0X72) .................112
FRAME CP-BIT ERRORS - ONE-SECOND ACCUMULATOR REGISTER - LSB (ADDRESS = 0X73) ..................112
LINE INTERFACE DRIVE REGISTER (ADDRESS = 0X80) ..............................................................................112
LINE INTERFACE SCAN REGISTER (ADDRESS = 0X81)...............................................................................115
HDLC CONTROL REGISTER (ADDRESS = 0X82) .......................................................................................116
2.4 THE LOSS OF CLOCK ENABLE FEATURE ........................................................................................................... 117
FRAMER I/O CONTROL REGISTER (ADDRESS = 0X01)...............................................................................117
2.5 USING THE PMON HOLDING REGISTER ............................................................................................................ 117
2.6 THE INTERRUPT STRUCTURE WITHIN THE FRAMER MICROPROCESSOR INTERFACE SECTION ............................... 117
TABLE 5: LIST OF ALL OF THE POSSIBLE CONDITIONS THAT CAN GENERATE INTERRUPTS WITHIN EACH CHANNEL OF THE XRT72L52
FRAMER DEVICE ...............................................................................................................................................118
TABLE 6: A LISTING OF THE XRT72L52 FRAMER DEVICE INTERRUPT BLOCK REGISTERS (FOR DS3 APPLICATIONS) ...........118
TABLE 7: A LISTING OF THE XRT72L52 FRAMER DEVICE INTERRUPT BLOCK REGISTERS (FOR E3, ITU-T G.832 APPLICATIONS)
119
TABLE 8: A LISTING OF THE XRT72L52 FRAMER DEVICE INTERRUPT BLOCK REGISTER (FOR E3, ITU-T G.751 APPLICATIONS)
119
BLOCK INTERRUPT STATUS REGISTER (ADDRESS = 0X05)........................................................................120
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04)........................................................................120
TABLE 9: INTERRUPT SERVICE ROUTINE GUIDE (FOR DS3 APPLICATIONS) ........................................................................ 121
TABLE 10: INTERRUPT SERVICE ROUTINE GUIDE (FOR E3, ITU-T G.832 APPLICATIONS) ................................................... 121
TABLE 11: INTERRUPT SERVICE ROUTINE GUIDE (FOR E3, ITU-T G.751 APPLICATIONS) ................................................... 121
2.6.1 Automatic Reset of Interrupt Enable Bits.............................................................................................. 121
2.6.2 One-Second Interrupts ......................................................................................................................... 122
3.0 The Line Interface and scan section ...............................................................................................123
Figure 27. XRT72L52 DS3/E3 Framer Interfaced to the XRT73L02A DS3/E3/STS-1 LIU ........................................... 123
3.1 BIT-FIELDS WITHIN THE LINE INTERFACE DRIVE REGISTER ................................................................................ 123
LINE INTERFACE DRIVE REGISTER (ADDRESS = 0X80) .......................................................................123
TABLE 12: THE RELATIONSHIP BETWEEN THE STATES OF RLOOP, LLOOP AND THE RESULTING LOOP-BACK MODE WITH THE
XRT73L02A ................................................................................................................................................... 125
3.2 BIT-FIELDS WITHIN THE LINE INTERFACE SCAN REGISTER ................................................................................. 126
LINE INTERFACE SCAN REGISTER (ADDRESS = 0X81).........................................................................126
4.0 DS3 Operation of the XRT72L52 ......................................................................................................128
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) .......................................................................128
4.1 DESCRIPTION OF THE DS3 FRAMES AND ASSOCIATED OVERHEAD BITS ............................................................. 128
Figure 28. DS3 Frame Format for C-bit Parity .............................................................................................................. 128
Figure 29. DS3 Frame Format for M13......................................................................................................................... 129
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) .......................................................................129
TABLE 13: BIT 2 SETTING WITHIN THE FRAMER OPERATING MODE REGISTER AND THE RESULTING DS3 FRAMING FORMAT 129
TABLE 14: C-BIT FUNCTIONS FOR THE C-BIT PARITY DS3 FRAME FORMAT ....................................................................... 130
4.1.1 Frame Synchronization Bits (Applies to both M13 and C-bit Parity Framing Formats) ........................ 130
4.1.2 Performance Monitoring/Error Detection Bits (Parity) .......................................................................... 130
4.1.3 Alarm and Signaling-Related Overhead Bits ........................................................................................ 131
4.1.4 The Data Link Related Overhead Bits .................................................................................................. 132
4.2 THE TRANSMIT SECTION OF THE XRT72L52 (DS3 MODE OPERATION) ............................................................. 132
Figure 30. The XRT72L52 Transmit Section configured to operate in the DS3 Mode .................................................. 133
4.2.1 The Transmit Payload Data Input Interface Block ................................................................................ 134
Figure 31. The Transmit Payload Data Input Interface Block ....................................................................................... 134
TABLE 15: DESCRIPTIONS FOR THE PINS ASSOCIATED WITH THE TRANSMIT PAYLOAD DATA INPUT INTERFACE .................... 134
Figure 32. The Terminal Equipment being interfaced to the Transmit Payload Data Input Interface block for Mode 1(Serial/
Loop-Timed) Operation.................................................................................................................................. 136
Figure 33. Behavior of the Terminal Interface signals between the Transmit Payload Data Input Interface block of the
XRT72L52 and the Terminal Equipment (Mode 1 Operation)........................................................................ 137
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) .......................................................................138
Figure 34. The Terminal Equipment being interfaced to the Transmit Payload Data Input Interface block for Mode 2 (Serial/
Local-Timed/Frame-Slave) Operation ........................................................................................................... 139
Figure 35. Behavior of the Terminal Interface signals between the XRT72L52 and the Terminal Equipment (Mode 2
Operation)...................................................................................................................................................... 140
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) .......................................................................140
Figure 36. The Terminal Equipment being interfaced to the Transmit Payload Data Input Interface block for Mode 3 (Serial/
Local-Timed/Frame-Master) Operation ......................................................................................................... 141
Figure 37. Behavior of the Terminal Interface signals between the XRT72L52 and the Terminal Equipment (DS3 Mode 3
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