XR72L52 Datasheet, PDF (60/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
FIGURE 26. MICROPROCESSOR INTERFACE TIMING - MOTOROLA-TYPE PROGRAMMED I/O WRITE OPERATION
ALE_AS
A[8:0]
CS
D[7:0]
RD_DS
W R_R/W
RDY_DTCK
Address of Target Register
Data to be W ritten
2.3 ON-CHIP REGISTER ORGANIZATION
The Microprocessor Interface section allows the user to do the following.
• Configure the Framer into a wide variety of operating modes
• Employ various features of the Framer
• Perform status monitoring
• Enable/Disable and service Interrupt Conditions
All of these things are accomplished by reading from and writing to the many on-chip registers. Table 4 lists
each of these registers and their corresponding address locations within the Framer Address space.
2.3.1 Framer Register Addressing
The array of on-chip registers consists of a variety of register types. These registers are denoted in Table 4,
as follows.
RO - Read Only Registers.
R/W - Read/Write Registers
RUR - Reset-upon-Read Registers
Some of these registers consists of both RO and R/W bit-fields. The bit-format and definitions for each of these
registers are presented in Section 2.3.2.
TABLE 4: REGISTER ADDRESSING OF THE FRAMER PROGRAMMER REGISTERS
ADDRESS
REGISTER NAME
POWER UP
DEFAULT VALUE
HEX
REGISTER TYPE
DEFAULT VALUE
0x00
Operating Mode register (E3 G.751 is default)
b00101011
0x2B
R/W
0x01
I/O Control Register
b10100000
0xA0
R/W, RO
0x02
Part Number Register (XRT72L52)
b00001000
0x08
RO
0x03
Version Number Register (Device Dependent)
b00000011
0x03
RO
0x04
Block Interrupt Enable Register
b00000000
0x00
R/W
0x05
Block Interrupt Status Register
b00000001
0x01
RO
0x06-0x0B Reserved
0x0C Test Register
b00000000
0x00
R/W, RO
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