XR72L52 Datasheet, PDF (477/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
FIGURE 204. AN OUTBOUND HDLC FRAME WHEN CRC-16 IS SELECTED
XRT72L52
REV. 1.0.1
CRC-16
Trailer
User Supplied Data
HDLC Frame
Once the outbound HDLC frame has been formed, then it will be transmitted to the remote terminal equipment
via payload bits of the outbound DS3 or E3 frames.
If the user’s terminal equipment does not supply any more data which needs to be encapsulated into the out-
bound HDLC frame and transmitted to the remote terminal equipment, then the Transmit HDLC Controller
block begins transmitting a constant stream of flag sequence octets (0x7E). These flag sequence octets will al-
so be transmitted to the remote terminal equipment via the payload bits of the outbound DS3 or E3 frames.
8.2.2 Operating the Receive HDLC Controller Block
The Receive HDLC Controller block within the XRT72L52 consists of the following pins:
TABLE 90: DESCRIPTION OF EACH OF THE RECEIVE HDLC CONTROLLER PINS
PIN NAME
RxIdle
Val_FCS
RxHDLCClk
RxHDLCData[7:0]
TYPE
DESCRIPTION
O ^{Receive Idle (Flag Sequence) Indicator Signal}
The combination of the RxIdle and Val_FCS output signals are used to convey information
about data that is being received via the Receive HDLC Controller block.
If RxIdle = "High":
The Receive HDLC Controller block pulses this output pin "High" any time the flag se-
quence is present on the RxHDLCDat[7:0] output data bus.
If RxIdle and Val_FCS are both "High":
The Receive HDLC Controller block has received a complete HDLC frame and has deter-
mined that the FCS value within this HDLC frame is valid.
If RxIdle is "High" and Val_FCS is "Low":
The Receive HDLC Controller block has received a complete HDLC frame and has deter-
mined that the FCS value within this HDLC frame is invalid.
If RxIdle is "Low" and Val_FCS is "High":
The Receive HDLC Controller block has received an ABORT sequence.
O ^{Valid FCS Indicator Signal}
Please see description above.
O ^{Receive HDLC Controller Clock Output signal:}
The Receive HDLC Controller block outputs data via the RxHDLCDat[7:0] output pins upon
the rising edge of this clock signal. The user is advised to configure the terminal equipment
circuitry to sample the contents of the RxHDLCDat[7:0] output pins upon the falling edge of
this clock signal.
I ^{Receive HDLC Controller - Output Data Bus:}
The Receive HDLC Controller block outputs data via these output pins upon the rising edge
of the RxHDLCClk clock signal. The user is advised to configure the terminal equiment cir-
cuitry to sample the contents of this data bus upon the falling edge of this clock signal.
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