XR72L52 Datasheet, PDF (69/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
2.3.2.6 Block Interrupt Status Register
BLOCK INTERRUPT STATUS REGISTER (ADDRESS = 0X05)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
RxDS3/E3
Interrupt
Status
Not Used
RO
RO
RO
RO
RO
0
0
0
0
0
BIT 2
RO
0
XRT72L52
REV. 1.0.1
BIT 1
TxDS3/E3
Interrupt
Status
RO
0
BIT 0
One-Second
Interrupt
Status
RUR
1
Bit 7 - RxDS3/E3 Interrupt Status Indicator
This Read-Only bit-field indicates whether or not a Receive-Section related interrupt has been requested and
is awaiting service.
If this bit-field is set to "0", then there are no Receive-Section related interrupts awaiting service. Conversely, if
this bit-field is set to "1", then there is at least one Receive Section related interrupt, awaiting service.
If this bit-field is set to "1", then the µC/µP must read the Source-Level Interrupt Status register in order to clear
this bit-field.
Bit 1 - TxDS3/E3 Interrupt Status Indicator
This Read-Only bit-field indicates whether or not a Transmit-Section related interrupt has been requested and
is awaiting service.
If this bit-field is set to "0", then there are no Transmit-Section related interrupts awaiting service. Conversely,
if this bit-field is set to "1", then there is at least one Transmit Section related interrupt, awaiting service.
If this bit-field is set to "1", then the µC/µP must read the Source-Level Interrupt Status register in order to clear
this bit-field.
Bit 0 - One-Second Interrupt Status
This Reset-upon-Read bit field indicates whether or not a One-Second interrupt has been requested and is
awaiting service.
If this bit-field is set to "0", then the One-Second interrupt is not awaiting service. Conversely, if this bit-field is
set to "1", then the One-Second interrupt is awaiting service.
This bit-field will be cleared immediately after the µC/µP has read this register.
2.3.2.7 Test Register
TEST REGISTER (ADDRESS = 0X0C)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TxOH Source Rx Payload Tx Payload Rx PRBS
Select Clock Enable Clock Enable
Lock
Rx PRBS
Enable
Tx PRBS
Enable
Reserved
R/W
R/W
R/W
RO
R/W
R/W
RO
RUR
0
0
0
0
0
0
0
0
Bit 7 - TxOH Source Select
This Read/Write bit-field permits the user to configure the Transmit Section of the channel to accept overhead
bits/bytes via the TxSer[n]or TxNib[3:0][n] input pins.
Setting this bit-field to “1” configures the Transmit Section of the channel to accept overhead bits/bytes via ei-
ther the TxSer[n] or TxNib[3:0][n]input pins.
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