XR72L52 Datasheet, PDF (217/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L52
REV. 1.0.1
RX DS3 STATUS REGISTER (ADDRESS = 0X11)
BIT 7
RO
0
BIT 6
Not Used
RO
0
BIT 5
RO
0
BIT 4
Rx FERF
RO
1
BIT 3
RxAIC
RO
X
BIT2
BIT 1
BIT 0
RxFEBE [2] RxFEBE [1] RxFEBE [0]
RO
RO
RO
X
X
X
This bit-field will remain asserted for the duration that the Yellow Alarm condition exists.
2. The Receive DS3 Framer block will also generate a Change in FERF Status interrupt to the µP/µC. Con-
sequently, the Receive DS3 Framer block will also assert the FERF Interrupt Status bit, within the Rx DS3
Interrupt Status Register, as depicted below.
RX DS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13)
BIT 7
BIT 6
BIT 5
BIT 4
CP-Bit Error LOS Interrupt AIS Interrupt
Interrupt
Status
Status
Status
IDLE Inter-
rupt Status
RUR
RUR
RUR
RUR
0
X
X
X
BIT 3
BIT2
FERF Inter- AIC Interrupt
rupt Status
Status
BIT 1
OOF Inter-
rupt Status
RUR
1
RUR
X
RUR
X
BIT 0
P-Bit Inter-
rupt Status
RUR
X
The Receive DS3 Framer block will clear the FERF condition, when it starts to receive Receive DS3 Frames
that have its X bits set to 1.
NOTE: The FERF indicator is frequently referred to as the Yellow Alarm.
4.3.2.5.5 The Detection of the FEBE Events
As described in Section 4.2.4.2.1.9, a given Terminal Equipment will set the three FEBE (Far-End Block Error)
bit-fields to the value [1, 1, 1] (e.g., all of the FEBE bits are set to “1”) within the outbound DS3 frames if, all of
the following conditions are true about the incoming DS3 line signal.
• The Receive Circuitry (within the Terminal Equipment) detects no P-Bit Errors.
• The Receive Circuitry (within the Terminal Equipment) detects no CP-Bit Errors.
If the Receive Section of the Terminal Equipment detects any P or CP bit errors, then the Transmit Section of
the Terminal Equipment will set the three FEBE bits (within the outbound DS3 data stream) to a value other
than [1, 1, 1].
How does the Receive DS3 Framer block (within the XRT72L52) respond when it receives a DS3 frame with all
three (3) of its FEBE bit-fields set to “1”?
As mentioned above, the Terminal Equipment will transmit DS3 frames, with the FEBE bits set to [1, 1, 1], dur-
ing un-erred conditions. Hence, if the Receive DS3 Framer block (within the XRT72L52 Framer IC) receives
DS3 frames with the FEBE bits set to [1, 1, 1] it will interpret this event as an un-erred event, and will continue
normal operation.
However, if the Receive DS3 Framer block receives a DS3 frame with the FEBE bits set to a value other than
[1, 1, 1], then it will increment the PMON FEBE Event Count Registers (which are located at address locations
0x58 and 0x59 within the Framer Address space).
4.3.2.5.6 Detection of Change in the AIC State
Section 4.1 indicates that the AIC (Application Identification Channel) bit-field is the third overhead bit, within F-
Frame # 1. This particular bit-field is set to “1” for the C-Bit Parity Framing Format, and is set to “0” for the M13
Framing Format.
Hence, a given Terminal Equipment receiving a DS3 data stream can identify the framing format of this DS3
data stream, by reading the value fo the AIC bit-field. The Receive DS3 Framer block permits the user’s Micro-
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