XR72L52 Datasheet, PDF (207/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L52
REV. 1.0.1
FIGURE 65. ILLUSTRATION OF TWO EXAMPLES OF B3ZS DECODING
Data 1 0 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 1
00 V
Line Signal
RxPOS
RxNEG
B 0V
4.3.1.2.3 Line Code Violations
The Receive DS3 LIU Interface block will also check the incoming DS3 data stream for line code violations.
For example, when the Receive DS3 LIU Interface block detects a valid bipolar violation (e.g., in B3ZS line
code), it will substitute three zeros into the binary data stream. However, if the bipolar violation is invalid, then
an LCV (Line Code Violation) is flagged and the PMON LCV Event Count Register (Address = 0x50 and 0x51)
will also be incremented. Additionally, the LCV-One Second Accumulation Registers (Address = 0x6E and
0x6F) will be incremented. For example: If the incoming DS3 data is B3ZS encoded, the Receive DS3 LIU In-
terface block will also increment the LCV One Second Accumulation Register if three (or more) consecutive
zeros are received.
4.3.1.2.4 RxLineClk Clock Edge Selection
The incoming unipolar or bipolar data, applied to the RxPOS and the RxNEG input pins are clocked into the
Receive DS3 LIU Interface block via the RxLineClk signal. The Framer IC allows the user to specify which
edge (e.g, rising or falling) of the RxLineClk signal will sample and latch the signal at the RxPOS and RxNEG
input signals into the Framer IC. This feature was included in the XRT72L52 design to insure that the user can
always meet the RxPOS and RxNEG to RxLineClk set-up and hold time requirements. This selection is made
by writing the appropriate data to bit 1 of the I/O Control Register, as depicted below.
I/O CONTROL REGISTER (ADDRESS = 0X01)
BIT 7
Disable
TxLOC
R/W
1
BIT 6
LOC
RO
0
BIT 5
Disable
RxLOC
R/W
1
BIT 4
AMI/ZeroSup
R/W
0
BIT 3
Unipolar/
Bipolar
R/W
0
BIT2
BIT 1
TxLine CLK RxLine CLK
Invert
Invert
R/W
R/W
0
0
BIT 0
Reframe
R/W
0
Table 33 depicts the relationship between the value of this bit-field to the sampling clock edge of RxLineClk.
191