 English |
|
|
|
|
|
|
|
| XR72L52 Datasheet, PDF (304/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER | |||
| |||
| ◁ |
XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
NOTE: The user will typically make the selection based upon the set-up and hold time requirements of the Transmit LIU IC.
FIGURE 113. WAVEFORM/TIMING RELATIONSHIP BETWEEN TXLINECLK, TXPOS AND TXNEG - TXPOS AND
TXNEG ARE CONFIGURED TO BE UPDATED ON THE RISING EDGE OF TXLINECLK
t32
TxLineClk
t30
t33
TxPOS
TxNEG
FIGURE 114. WAVEFORM/TIMING RELATIONSHIP BETWEEN TXLINECLK, TXPOS AND TXNEG - TXPOS AND
TXNEG ARE CONFIGURED TO BE UPDATED ON THE FALLING EDGE OF TXLINECLK
t32
TxLineClk
t31
t33
TxPOS
TxNEG
5.2.6 Transmit Section Interrupt Processing
The Transmit Section of the XRT72L52 can generate an interrupt to the Microprocessor/Microcontroller for the
following reasons.
⢠Completion of Transmission of LAPD Message
5.2.6.1 Enabling Transmit Section Interrupts
The Interrupt Structure, within the XRT72L52 contains two hierarchical levels:
⢠Block Level
⢠Source Level
The Block Level
The Enable State of the Block Level for the Transmit Section Interrupts dictates whether or not interrupts (en-
abled) at the source level, are actually enabled.
288
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese