XR72L52 Datasheet, PDF (470/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
During system configuration, the user is expected to specify the Payload Type value that is expected of the Re-
ceive E3 Framer to receive (within each E3 frame), by writing this value into the RxPLDExp[2:0] bit-fields within
the Rx E3 Configuration & Status Register - 1, as indicated below..
RXE3 CONFIGURATION & STATUS REGISTER 1 (ADDRESS = 0X10)
BIT 7
BIT 6
RxPLDType[2:0]
BIT 5
RO
RO
RO
0
0
0
BIT 4
RxFERF
Algo
RO
0
BIT 3
RxTMark
Algo
RO
0
BIT 2
BIT 1
RxPLDExp[2:0]
BIT 0
R/W
R/W
R/W
0
0
0
As long as the Receive E3 Framer block receives E3 frames that contains this Payload Type value, no interrupt
will be generated. However, the instant that it receives an E3 frame, that contains a different Payload Type val-
ue, then the XRT72L52 Framer IC will generate this interrupt.
RXE3 CONFIGURATION & STATUS REGISTER 1 (ADDRESS = 0X10)
BIT 7
BIT 6
RxPLDType[2:0]
BIT 5
RO
RO
RO
0
0
0
BIT 4
RxFERF
Algo
RO
0
BIT 3
RxTMark
Algo
RO
0
BIT 2
BIT 1
RxPLDExp[2:0]
BIT 0
R/W
R/W
R/W
0
0
0
Enabling and Disabling the Detection of Payload Type Mismatch Interrupt.
The user can enable or disable the Detection of Payload Type Mismatch Interrupt by writing the appropriate
data into Bit 0 (RxPld Mis Interrupt Enable), within the Rx E3 Interrupt Enable Register - 2, as indicated below.
RXE3 INTERRUPT ENABLE REGISTER - 2 (ADDRESS = 0X13)
BIT 7
Not Used
RO
0
BIT 6
TTB
Change
Interrupt
Enable
R/W
0
BIT 5
Not Used
RO
0
BIT 4
FEBE
Interrupt
Enable
R/W
0
BIT 3
FERF
Interrupt
Enable
R/W
0
BIT 2
BIP-8
Error Interrupt
Enable
R/W
0
BIT 1
Framing
Byte Error
Interrupt
Enable
R/W
0
BIT 0
RxPld
Mis
Interrupt
Enable
R/W
X
Setting this bit-field to “1 enables the Detection of Payload Type Mismatch Interrupt. Conversely, setting this
bit-field to “0” disables the Detection of Payload Type Mismatch Interrupt.
Servicing the Detection of Payload Type Mismatch Interrupt
Whenever the XRT72L52 Framer IC generates this interrupt, it will do the following.
• It will assert the Interrupt Request output pin (Int) by driving it "Low".
• It will set Bit 0 (RxPld Mis Interrupt Status), within the Rx E3 Interrupt Enable Register -2 to “1”, as indicated
below.
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