XR72L52 Datasheet, PDF (181/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L52
REV. 1.0.1
If the TxFEAC processor is disabled, the FEAC bit contains a “1” which the remote Rx side interprets as an idle
FEAC message.
Figure 49 presents a flow chart depicting how to use the Transmit FEAC Processor.
NOTE: The FEAC processor starts transmitting the last FEAC message when enabled. Execute the “Initiate Transmission
of the Outbound FEAC Message” step without delay to prevent unintended incorrect transmission. Rx FEAC prossecor val-
idates a FEAC code upon receiving the same code 8 times.
FIGURE 49. A FLOW CHART DEPICTING HOW TO TRANSMIT A FEAC MESSAGE VIA THE FEAC TRANSMITTER
START
1
WriteSix-Bit Outbound FEAC Value Into
the TxDS3 FEAC Register
The address is located at 0x32.
Enable the Transmit FEAC Processor
This is accom plished by writing xxxxx1xx
into the TxDS3 FEAC Configuration and
Status Register.
NOTE:
The FEAC processor starts transmitting
the last FEAC message when enabled.
Execute the “Initiate Transmission of
the Outbound FEAC Message” step
without delay to prevent unintended
incorrect transmission. Rx FEAC
prossecor validates a FEAC code upon
receiving the same code 8 times.
Initiate Transmission of the outbound
FEAC Message
This is accom plished by writing xxxxx1xx
into the TxDS3 FEAC Configuration and
Status Register.
Transm it FEAC Processor Encapsulates the Outbound
FEAC value into a 16 bit Fram ing Structure.
Transmit FEAC Processor Proceeds to Insert the 16 bit
Message (in a bit-by-bit Manner) into the FEAC Fields
of each outbound DS3 Frame.
Has the
NO ^{16-bit FEAC Mesage} YES
been transm itted to
the remote terminal
10 times ?
Is Transm ission
of the 16-bit
FEAC Message
com plete?
YES
NO
Generate the Transmit FEAC Interrupt
Invoke the Transmit FEAC Interrupt
Service Routine
1
NOTE: For a detailed description of the Receive FEAC Processor within the Receive DS3 HDLC Controller block, please
see Section 4.3.3.1.
4.2.3.2 Message-Oriented Signaling (e.g., LAP-D) processing via the Transmit DS3 HDLC Controller
The LAPD Transmitter within the Transmit DS3 HDLC Controller Block allows the user to transmit Path Mainte-
nance Data Link (PMDL) messages to the remote terminal via the outbound DS3 Frames. The message bits
are inserted into and carried by the 3 DL bit fields of F-Frame #5 within each DS3 M-frame. The on-chip LAPD
transmitter supports both the 76 byte and 82 byte length message formats and the Framer allocates 88 bytes
of on-chip RAM (e.g., the Transmit LAPD Message buffer) to store the message to be transmitted. The mes-
sage format complies with ITU-T Q.921 (LAP-D) protocol with different addresses and is presented below in
Figure 50.
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