XR72L52 Datasheet, PDF (72/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
NOTE: For more information on Framing with Parity, refer to Section 4.3.2.2.
Bit 1 - F Sync Algo(rithim Select)
This Read/Write bit-field, in conjunction with Bits 0 and 2 of this register, allows the user to completely define
the Frame Maintenance Criteria of the Receive DS3/E3 Framer block. This particular bit-field allows the user
to define the Frame Maintenance Criteria as it applies to F-bits.
If the user writes a "1" to this bit-field, then the Receive DS3/E3 Framer block will declare an Out of Frame
(OOF) condition if 3 out of 16 F-Bits are in Error. If the user writes a "0" to this bit-field, then the Receive DS3/
E3 Framer block will declare an Out of Frame (OOF) condition if 6 out of 16 F-bits are in error.
NOTE: For more information on the use of this bit, and the Framing Maintenance operation of the Receive DS3/E3 Framer
block, refer to Section 4.3.2.2.
Bit 0 - M Sync Algo(rithm Select)
This Read/Write bit-field in conjunction with Bits 1 and 2 of this register, allows the user to completely define
the Frame Maintenance Criteria of the Receive DS3/E3 Framer block. This particular bit-field allows the user
to define the Frame Maintenance criteria, as it applies to M-bits.
If the user writes a "1" to this bit-field, then the Receive DS3/E3 Framer block will declare an Out of Frame
(OOF) condition if 3 out of 4 M-bits are in error. If the user writes a "0" to this bit-field, then the Receive DS3/E3
Framer block will ignore the occurrence of M-bit errors while operating in the Frame Maintenance mode.
NOTE: For more information on the use of this bit-field, and the Framing Maintenance operation of the Receive DS3/E3
Framer block, refer to Section 4.3.2.2.
2.3.2.9 Receive DS3 Status Register
RXDS3 STATUS REGISTER (ADDRESS = 0X11)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
RxFERF
RxAIC
RxFEBE[2:0]
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
1
0
0
0
0
Bit 4 - RxFERF Indicator
This Read Only bit-field indicates whether or not the Receive Section of the channel is declaring a FERF (Far-
End-Receive Failure) condition.
If this bit-field is set to "0", then the Receive Section (of the channel) is currently not declaring an FERF condi-
tion.
If this bit-field is set to "1", then the Receive Section (of the chip) is currently declaring an FERF condition.
NOTE: For more information on how the Receive Section of the channel declares the FERF condition, refer to
Section 4.3.2.5.4.
Bit 3 - RxAIC
This Read Only bit-field reflects the value of the AIC bit-field, within the incoming DS3 Frames, as detected by
the Receive DS3/E3 Framer block (within the channel). This bit-field is set to "1" if the incoming frame is deter-
mined to be in the C-bit Parity Format (AIC bit = 1) for at least 63 consecutive frames. This bit-field is set to "0"
if two (2) or more M-frames, out of the last 15 M-frames, contain a "0" in the AIC bit position.
Bits 2:0 - RxFEBE[2:0]
These Read-Only bit-fields reflect the FEBE value within the most recently received DS3 frame.
If these bit-fields are set to "111", then it indicates that the Remote Receiving Terminal is receiving DS3 frames
in an un-erred manner.
If these bit-fields are set to "011", then it indicates that the Remote Receiving Terminal has detected Framing or
Parity bit errors in the DS3 frames that it is receiving.
NOTE: For more information on FEBE (Far-End-Block Error), refer to Section 4.3.2.5.5.
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