XR72L52 Datasheet, PDF (139/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L52
REV. 1.0.1
The remaining registers, listed in Table 9, Table 10 and Table 11 will be presented in the discussion of the func-
tional blocks, within the XRT72L52 Framer IC. These discussions will present more details about the interrupt
causes and how to properly service. them.
3.0 THE LINE INTERFACE AND SCAN SECTION
The Line Interface and Scan Section of the XRT72L52 DS3/E3 Framer IC consists of 5 output pins, 3 input
pins, a Read/Write register, and a Read-Only register.
The purpose of the Line Interface Drive and Scan section is to permit the user to monitor and exercise control
over many aspects of the XRT73L02A DS3/E3/STS-1 LIU IC without having to develop the necessary off-chip
glue-logic.
Figure 27 presents a simple circuit schematic that depicts how the XRT72L52 DS3/E3 Framer IC could be in-
terfaced to the XRT73L02A DS3/E3/STS-1 LIU IC.
FIGURE 27. XRT72L52 DS3/E3 FRAMER INTERFACED TO THE XRT73L02A DS3/E3/STS-1 LIU
TxS ER
T xI n C lk
TxFram e
NIBINTF
RESETB
INTB
CSB
RW
DS
AS
INTB
A[8:0]
D[7:0]
VDD
RxS er
R xC lk
RxFram e
R xL O S
R xO O F
R xR E D
R xA I S
U1
45
43 ^TxSer/SndMsg
61 ^TxInClk
TxFram e
25
NibbleIntf
28
Reset
13
8 ^Int
7 ^CS
10 ^{W R_R/W}
9 ^RD_DS
6 ^ALE_AS
RDY_DTCK
15
16 ^A0
17 ^A1
18 ^A2
19 ^A3
20 ^A4
21 ^A5
22 ^A6
23 ^A7
A8
32
33 ^D0
34 ^D1
35 ^D2
36 ^D3
37 ^D4
38 ^D5
39 ^D6
D7
27
MOTO
86
88 ^RxSer/RxIdle
90
R xC lk
RxFram e
95
94 ^RxLOS
93 ^RxOOF
87 ^RxRED
RxA IS
XRT72L50
65
TxP OS
64
T xN E G
63
T xL in eC lk
79
DMO
78
ExtLOS
77
RLOL
69
LLOOP
70
RLOOP
68
TAOS
67
T xL ev
66
EncoDis
71
Req
U2
37
TPDATA
38
TNDATA
36
TCLK
4
DMO
24
RLOS
23
RLOL
14
LLB
15
RLB
2
TAOS
1
TxLE V
21
ENCODIS
12
REQDIS
76
RxP OS
75
R xN E G
74
R xL in eC lk
33
RPOS
32
RNEG
31
RCLK1
XRT73L00
41
TTIP
40
TRING
44
MTIP
43
MRING
1 ^R3 2
270
1 ^R4 2
270
R1
1
2
36
T
11 5
R2
1
2
36
4
8
1:
1
TTIP
TRING
8
RTIP
9
RRING
C1
1
2
0.01uF
R5
37.5
R6
37.5
1 ^T2 5
4
8
1:1
RTIP
RRING
3.1 BIT-FIELDS WITHIN THE LINE INTERFACE DRIVE REGISTER
As mentioned above, the Line Interface Drive and Scan section consists of five output pins and three input
pins. The logic state of the output pins are controlled by the contents within the Line Interface Drive register, as
depicted below.
LINE INTERFACE DRIVE REGISTER (ADDRESS = 0X80)
BIT 7
ILOOP
R/W
0
BIT 6
Not Used
RO
0
BIT 5
REQB
R/W
0
BIT 4
TAOS
R/W
0
BIT 3
ENCODIS
R/W
1
Bit 7 - ILOOP (Internal Remote Loop-back)
BIT 2
TxLEV
R/W
0
BIT 1
RLOOP
R/W
0
BIT 0
LLOOP
R/W
0
123