XR72L52 Datasheet, PDF (446/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
TABLE 85: THE RELATIONSHIP BETWEEN THE NUMBER OF RISING CLOCK EDGES IN RXOHCLK, (SINCE
RXOHFRAME WAS LAST SAMPLED "HIGH") TO THE E3 OVERHEAD BIT, THAT IS BEING OUTPUT VIA THE RXOH
OUTPUT PIN
NUMBER OF RISING CLOCK EDGES IN RXOHCLK
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
THE OVERHEAD BIT BEING OUTPUT BY THE
XRT72L52
TR Byte - Bit 2
TR Byte - Bit 1
TR Byte - Bit 0
MA Byte - Bit 7
MA Byte - Bit 6
MA Byte - Bit 5
MA Byte - Bit 4
MA Byte - Bit 3
MA Byte - Bit 2
MA Byte - Bit 1
MA Byte - Bit 0
NR Byte - Bit 7
NR Byte - Bit 6
NR Byte - Bit 5
NR Byte - Bit 4
NR Byte - Bit 3
NR Byte - Bit 2
NR Byte - Bit 1
NR Byte - Bit 0
GC Byte - Bit 7
GC Byte - Bit 6
GC Byte - Bit 5
GC Byte - Bit 4
GC Byte - Bit 3
GC Byte - Bit 2
GC Byte - Bit 1
GC Byte - Bit 0
Figure 192 presents the typical behavior of the Receive Overhead Data Output Interface block, when Method 1
is being used to sample the incoming E3 overhead bits.
430