M32C80 Datasheet, PDF (95/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
8. Clock Generation Circuit
8.5.3.1 Entering Stop Mode
Stop mode is entered when setting the CM10 bit in the CM1 register to "1" (all clocks stops). The
MCD4 to MCD0 bits in the MCD register become set to "010002" (divide-by-8 mode).
Enter stop mode after setting the followings.
• Initial Setting
Set each interrupt priority level after setting the exit priority level required to exit stop mode, con-
trolled by the RLVL2 to RLVL0 bits in the RLVL register, to "7".
• Before Entering stop mode
(1) Set the I flag to "0"
(2) Set the interrupt priority level of the interrupt being used to exit stop mode
(3) Set the interrupt priority levels of the interrupts, not being used to exit stop mode, to "0"
(4) Set IPL in the FLG register. Then set the exit priority level to the same level as IPL
Interrupt priority level of the interrupt used to exit stop mode > IPL = the exit priority level
(5) Set the PRC0 bit in the PRCR register to "1" (write enabled)
(6) Select the main clock as the CPU clock
• When the CPU clock source is the sub clock,
(a) set the CM05 bit in the CM0 register to "0" (main clock oscillates)
(b) set the CM07 bit in the CM0 register to "0" (clock selected by the CM21 bit divided by MCD
register setting)
• When the CPU clock source is the PLL clock,
(a) set the CM17 bit in the CM1 register to "0" (main clock)
(b) set the PLC07 bit in the PLC0 register to "0" (PLL off)
• When the CPU clock source is the on-chip oscillator clock,
(a) set MCD4 to MCD0 bits to "010002" (divide-by-8 mode)
(b) set the CM05 bit to "0" (main clock oscillates)
(c) set the CM21 bit in the CM2 register to "0" (clock selected by the CM17 bit)
(7) The oscillation stop detect function is used, set the CM20 bit in the CM2 register to "0" (oscilla-
tion stop detect fucntion disabled)
(8) Set the I flag to "1"
(9) Set the CM10 bit to "1" (all clocks stops)
• After Exiting Stop Mode
Set the exit priority level to "7" as soon as exiting stop mode.
8.5.3.2 Exiting Stop Mode
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Stop mode is exited by the hardware reset, NMI interrupt or peripheral function interrupts (key input
______
interrupt and INT interrupt).
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When the hardware reset or NMI interrupt, but not the peripheral function interrupts, is used to exit wait
mode, set all ILVL2 to ILVL0 bits in the interrupt control registers for the peripheral function interrupt to
"0002" (interrupt disabled) before setting the CM10 bit to "1" (all clocks stops).
Rev. 1.00 Nov. 01, 2005 Page 76 of 330
REJ09B0271-0100