M32C80 Datasheet, PDF (173/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
14. Timer (Timer B)
Timer Bi Mode Register (i=0 to 5)
(Pulse Period / Pulse Width Measurement Mode)
b7 b6 b5 b4 b3 b2 b1 b0
10
Symbol
Address
After reset
TB0MR to TB5MR 035B16, 035C16, 035D16, 031B16, 031C16, 031D16 00XX 00002
Bit
Symbol
Bit Name
TMOD0 _{Operating Mode}
TMOD1 ^{Select Bit}
MR0
MR1
Measurement Mode
Select Bit⁽¹⁾
Function
RW
b1b0
RW
1 0: Pulse period measurement mode,
Pulse width measurement mode _RW
b3b2
0 0: Pulse period measurement 1 _RW
0 1: Pulse period measurement 2
1 0: Pulse width measurement
RW
1 1: Do not set to this value
TB0MR, TB3MR registers:
Set to "0" in pulse period/pulse width measurement mode
RW
MR2 _{TB1MR, TB2MR TB4MR, TB5MR registers:}
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
MR3
Timer
Bi
Overflow
Flag⁽²⁾
0:
1:
No overflow
Overflow
RO
b7b6
TCK0
0 0: f1
RW
Count Source
0 1: f8
Select Bit
1 0: f2n(3)
TCK1
1 1: fC32
RW
NOTES:
1. The MR1 and MR0 bits selects the following measurements.
Pulse period measurement 1 (the MR1 and MR0 bits are set to "002"):
Measures between the falling edge and the next falling edge of a pulse to be measured
Pulse period measurement 2 (the MR1 and MR0 bits are set to "012"):
Measures between the rising edge and the next rising edge of a pulse to be measured
Pulse width measurement (the MR1 and MR0 bits are set to "102"):
Measures between a falling edge and the next rising edge of a pulse to be measured and
between the rising edge and the next falling edge of a pulse to be measured
2. The MR3 bit is indeterminate when reset.
To set the MR3 bit to "0", se the TBiMR register after the MR3 bit is set to "1" and one or more cycles
of the count source are counted, while the TBiS bits in the TABSR and TBSR registers are set to "1"
(starts counting).
The MR3 bit cannot be set to "1" by program.
3. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Figure 14.22 TB0MR to TB5MR Registers
Rev. 1.00 Nov. 01, 2005 Page 154 of 330
REJ09B0271-0100