M32C80 Datasheet, PDF (202/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
16. Serial I/O (UART)
16.2 Clock Asynchronous Serial I/O (UART) Mode
In UART mode, data is transmitted and received after setting a desired bit rate and data transfer format.
Table 16.6 lists specifications of UART mode.
Table 16.6 UART Mode Specifications
Item
Specification
Transfer Data Format • Character bit (transfer data) : selected from 7 bits, 8 bits, or 9 bits long
• Start bit: 1 bit long
• Parity bit: selected from odd, even, or none
• Stop bit: selected from 1 bit or 2 bits long
Transfer Clock
Transmit/Receive Control
• The CKDIR bit in the UiMR register is set to "0" (internal clock selected):
fj/16(m+1) fj = f1, f8, f2n(1) m: setting value of the UiBRG register , 0016 to FF16
• The CKDIR bit is set to "1" (external clock selected):
fEXT/16(m+1)
fEXT: clock applied to the CLKi pin
_______
_______
_______ _______
Select from CTS function, RTS function or CTS/RTS function disabled
Transmit Start Condition To start transmitting, the following requirements must be met:
- Set the TE bit in the UiC1 register to "1" (transmit enabled)
- Set the TI bit in the UiC1 register to "0" (data in the UiTB register)
_______
_______
- Apply a low-velel ("L") signal to the CTSi pin when the CTS function is selected
Receive Start Condition To start receiving, the following requirements must be met:
- Set the RE bit in the UiC1 register to "1" (receive enabled)
- The start bit is detected
Interrupt Request
While transmitting, the following condition can be selected:
Generation Timing
- The UiIRS bit in the UiC1 register is set to "0" (no data in the UiTB register):
when data is transferred from the UiTB register to the UARTi transmit register (transfer started)
- The UiIRS bit is set to "1" (transmission completed):
when data transmission from the UARTi transfer register is completed
While receiving
Error Detect
when data is transferred from the UARTi receive register to the UiRB register (reception completed)
• Overrun error⁽²⁾
This error occurs when the bit before the last stop bit of the next received data is read
prior to reading the UiRB register (the first stop bit when selecting 2 stop bits)
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
When parity is enabled, this error occurs when the number of "1" in parity and charac-
ter bits does not match the number of "1" set
• Error sum flag
This flag is set to "1" when any of an overrun, framing or parity errors occur
Selectable Function
• LSB first or MSB first
Selectable from data transmission or reception in either bit 0 or in bit 7
•Serial data logic inverse
Logic values of data to be transmitted and received data are inversed. The start bit
and stop bit are not inversed
•TxD and RxD I/O polarity Inverse
TxD pin output and RxD pin input are inversed. All I/O data levels are also inversed
NOTES:
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
2. If an overrun error occurs, the UiRB register is indeterminate. The IR bit setting in the SiRIC register does not
change to "1" (interrupt requested).
Rev. 1.00 Nov. 01, 2005 Page 183 of 330
REJ09B0271-0100