M32C80 Datasheet, PDF (164/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
14. Timer (Timer A)
Timer Ai Mode Register (i=0 to 4) (Pulse Width Modulator Mode)
b7 b6 b5 b4 b3 b2 b1 b0
0 11
Symbol
Address
TA0MR to TA4MR 035616, 035716, 035816, 035916, 035A16
After Reset
0016
Bit
Symbol
Bit Name
Function
RW
TMOD0
TMOD1
Operating Mode
Select Bit
RW
b1b0
1 1: Pulse width modulation (PWM)
mode
RW
(b2)
MR1
MR2
MR3
Reserved Bit
Set to "0"
RW
External Trigger Select
Bit⁽¹⁾
0: Falling edge of input signal to TAiIN pin
1: Rising edge of input signal to TAiIN pin
RW
Trigger Select Bit
0: The TAiS bit is enabled
1: Selected by the TAiTGH and TAiTGL RW
bits
16/8-Bit PWM Mode
Select Bit
0: Functions as a 16-bit pulse width modulator
1: Functions as an 8-bit pulse width modulator
RW
TCK0
b7b6
0 0: f1
RW
Count Source
0 1: f8
Select Bit
1 0: f2n(2)
TCK1
1 1: fC32
RW
NOTES:
1. MR1 bit setting is enabled only when the TAiTGH and TAiTGL bits in the TRGSR register are set to
"002" (input to the TAiIN pin). The MR1 bit can be set to either "0" or "1" when the TAiTGH and
TAiTGL bits are set to "012" (TB2 overflow and underflow), "102" (TAi overflow and underflow) or
"112" (TAi overflow and underflow).
2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Figure 14.13 TA0MR to TA4MR Registers
Rev. 1.00 Nov. 01, 2005 Page 145 of 330
REJ09B0271-0100