M32C80 Datasheet, PDF (152/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
14. Timer (Timer A)
Up/Down Flag⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UDF
Address
034416
After Reset
0016
Bit
Symbol
Bit Name
Function
RW
TA0UD
Timer A0
Up/Down Flag⁽²⁾
0: Decrement
1: Increment
RW
TA1UD
Timer A1
Up/Down Flag⁽²⁾
0: Decrement
1: Increment
RW
TA2UD
Timer A2
Up/Down Flag⁽²⁾
0: Decrement
1: Increment
RW
TA3UD
Timer A3
Up/Down Flag⁽²⁾
0: Decrement
1: Increment
RW
TA4UD
Timer A4
Up/Down Flag⁽²⁾
0: Decrement
1: Increment
RW
Timer A2 Two-Phase ^{0: Disables two-phase pulse signal}
TA2P
Pulse Signal Processing
Function Select Bit⁽³⁾
processing function
1: Enables two-phase pulse signal
processing function
WO
Timer A3 Two-Phase ^{0: Disables two-phase pulse signal}
TA3P
Pulse Signal Processing
Function Select Bit⁽³⁾
processing function
1: Enables two-phase pulse signal
processing function
WO
Timer A4 Two-Phase ^{0: Disables two-phase pulse signal}
TA4P
Pulse Signal Processing
Function Select Bit⁽³⁾
processing function
1: Enables two-phase pulse signal
processing function
WO
NOTES:
1. Use the MOV instruction to set the UDF register.
2. This bit is enabled when the MR2 bit in the TAiMR register (i=0 to 4) is set to "0" (the UDF register
causes increment/decrement switching) in event counter mode.
3. Set this bit to "0" when not using the two-phase pulse signal processing function.
One-Shot Start Flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ONSF
Address
034216
After Reset
0016
Bit
Symbol
Bit Name
Function
RW
TA0OS
Timer A0 One-Shot
Start Flag⁽¹⁾
0: In an idle state
1: Starts the timer
RW
TA1OS
Timer A1 One-Shot
Start Flag⁽¹⁾
0: In an idle state
1: Starts the timer
RW
TA2OS
Timer A2 One-Shot
Start Flag⁽¹⁾
0: In an idle state
1: Starts the timer
RW
TA3OS
Timer A3 One-Shot
Start Flag⁽¹⁾
0: In an idle state
1: Starts the timer
RW
TA4OS
Timer A4 One-Shot
Start Flag⁽¹⁾
0: In an idle state
1: Starts the timer
RW
TAZIE ^{Z-Phase Input Enable}
Bit
TA0TGL
Timer A0 Event/Trigger
Select Bit
TA0TGH
NOTES:
1. When read, this bit is set to "0".
2. Overflow or underflow.
0: Disables Z-phase input
1: Enables Z-phase input
RW
b7b6
0 0: Selects an input to the TA0IN pin RW
0 1: Selects the TB2 overflows⁽²⁾
1 0: Selects the TA4 overflows⁽²⁾
1 1: Selects the TA1 overflows⁽²⁾
RW
Figure 14.6 UDF Register and ONSF Register
Rev. 1.00 Nov. 01, 2005 Page 133 of 330
REJ09B0271-0100