M32C80 Datasheet, PDF (74/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
7. Bus
_________
7.2.7 HOLD Signal
__________
The HOLD signal transfers bus privileges from the CPU to external circuits. When a low-level ("L") signal is
__________
applied to the HOLD pin, the microcomputer enters a hold state after bus access is completed. While the
__________
_________
HOLD pin is held "L", the microcomputer is in a hold state and the HLDA pin outputs an "L" signal.
Table 7.7 shows the microcomputer status in a hold state.
__________
Bus is used in the following priority order: HOLD, DMAC, CPU.
__________
HOLD > DMAC > CPU
Figure 7.12 Bus Priority Order
Table 7.7 Microcomputer Status in Hold State
Item
Status
Oscillation
RD Signal, WR Signal, Address Bus, Data Bus,
CS, BHE
Programmable I/O Ports
On
High-impedance
Maintains the same state as when HOLD signal was received
HLDA
Internal Peripheral Circuits
Outputs "L"
On (excluding the watchdog timer)
ALE Signal
Outputs "L"
7.2.8 External Bus Status when Accessing Internal Space
Table 7.8 shows external bus states when an internal space is accessed.
Table 7.8 External Bus States when Accessing Internal Space
Item
State when Accessing SFRs, Internal ROM, and Internal RAM
Address Bus
Holds address of external space last accessed
Data
Bus
When Reading High-impedance
When Writing High-impedance
RD, WR, WRL, WRH
Outputs "H"
BHE
Holds state of external space last accessed
CS
Outputs "H"
ALE
Outputs ALE
7.2.9 BCLK Output
The CPU clock operates the CPU. P53 outputs the CPU clock signal as BCLK when the PM07 bit in the
PM0 register is set to "0" (BCLK) and the CM01 and CM00 bits in the CM0 register are set to "002" (I/O
port P53).
No BCLK is output in single-chip mode. Refer to 8. Clock Generation Circuit for details.
Rev. 1.00 Nov. 01, 2005 Page 55 of 330
REJ09B0271-0100