M32C80 Datasheet, PDF (200/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
16. Serial I/O (Clock Synchronous Serial I/O)
16.1.1 Selecting CLK Polarity Selecting
As shown in Figure 16.11, the CKPOL bit in the UiC0 register (i=0 to 4) determines the polarity of the
transfer clock.
(1) When the CKPOL bit in the UiC0 register (i=0 to 4) is set to "0"
(Data is transmitted on the falling edge of the transfer clock and data is received on the rising edge)
"H"
CLKi _"L"
"H"
TXDi _"L"
"H"
RXDi _"L"
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
NOTES:
1. The CLKi pin is held high ("H") when no data is transferred.
2. The above applies when the UFORM bit in the UiC0 register is set to "0" (LSB first)
and the UiLCH bit in the UiC1 register is set to "0" (not inversed).
(2) When the CKPOL bit in the UiC0 register is set to "1"
(Data is transmitted on the rising edge of the transfer clock and data is received on the falling edge)
CLKi ^"H"
"L"
TXDi ^"H"
"L"
D0 D1 D2 D3 D4 D5 D6 D7
RXDi ^"H"
"L"
D0 D1 D2 D3 D4 D5 D6 D7
NOTES:
3. The CLKi pin is held low ("L") when no data is transferred.
4. The above applies when the UFORM bit in the UiC0 register is set to "0" (LSB first)
and the UiLCH bit in the UiC1 register is set to "0" (not inversed).
Figure 16.11 Transfer Clock Polarity
16.1.2 Selecting LSB First or MSB First
As shown in Figure 16.12, the UFORM bit in the UiC0 register (i=0 to 4) determines a data transfer format.
(1) When the UFORM bit in the UiC0 register (i=0 to 4) is set to "0"
(LSB first)
"H"
CLKi _"L"
"H"
TXDi _"L"
D0 D1 D2 D3 D4 D5 D6 D7
RXDi
"H"
"L"
D0 D1 D2 D3 D4 D5 D6 D7
NOTE:
1. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is
transmitted on the falling edge of the transfer clock and received on the rising
edge) and the UiLCH bit in the UiC1 register is set to "0" (not inversed).
(2) When the UFORM bit in the UiC0 register is set to "1" (MSB first)
"H"
CLKi _"L"
"H"
TXDi _"L"
"H"
RXDi _"L"
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
NOTE:
2. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is
transmitted on the falling edge of the transfer clock and received on the rising
edge) and the UiLCH bit in the UiC1 register is set to "0" (not inversed).
Figure 16.12 Transfer Format
Rev. 1.00 Nov. 01, 2005 ^{Page 181} of 330
REJ09B0271-0100