M32C80 Datasheet, PDF (118/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
10. Interrupts
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10.7 INT Interrupt
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External input generates the INTi interrupt (i = 0 to 5). The LVS bit in the INTiIC register selects either edge
sensitive triggering to generate an interrupt on any edge or level sensitive triggering to generate an inter-
rupt at an applied signal level. The POL bit in the INTiIC register determines the polarity.
For edge sensitive, when the IFSRi bit in the IFSR register is set to "1", an interrupt occurs on both rising
and falling edges of the external input. If the IFSRi bit is set to "1", set the POL bit in the corresponding
register to "0" (falling edge).
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For level sensitive, set the IFSRi bit to "0" (single edge). When the INTi pin input level reaches the level set
_______
in the POL bit, the IR bit in the INTiIC register is set to "1". The IR bit remains unchanged even if the INTi
_______
pin level is changed. The IR bit is set to "0" when the INTi interrupt is acknowledged or when the IR bit is
written to "0" by program.
Figure 10.10 shows the IFSR register.
External Interrupt Request Source Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IFSR
Address
031F16
After Reset
0016
Bit
Symbol
Bit Name
Function
RW
IFSR0
INT0 Interrupt Polarity
Select Bit⁽¹⁾
0: One edge
1 : Both edges
RW
INT1 Interrupt Polarity 0: One edge
IFSR1 _{Select Bit(1)}
1: Both edges
RW
IFSR2
INT2 Interrupt Polarity
Select Bit⁽¹⁾
0: One edge
1: Both edges
RW
INT3 Interrupt Polarity 0: One edge
IFSR3 _{Select Bit(1)}
1: Both edges
RW
IFSR4
INT4 Interrupt Polarity
select bit⁽¹⁾
0: One edge
1: Both edges
RW
IFSR5
INT5 Interrupt Polarity
Select Bit⁽¹⁾
0: One edge
1: Both edges
RW
IFSR6
UART0, UART3
Interrupt Source
Select Bit
0: UART3 bus conflict, start condition
detect, stop condition detect
1: UART0 bus conflict, start condition
RW
detect, stop condition detect
IFSR7
UART1, UART4
Interrupt Source
Select Bit
0: UART4 bus conflict, start condition
detect, stop condition detect
1: UART1 bus conflict, start condition
RW
detect, stop condition detect
NOTE:
1. Set this bit to "0" to select a level-sensitive triggering.
When setting this bit to "1", set the POL bit in the INTilC register (i = 0 to 5) to "0" (falling edge).
Figure 10.10 IFSR Register
Rev. 1.00 Nov. 01, 2005 Page 99 of 330
REJ09B0271-0100