M32C80 Datasheet, PDF (82/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
8. Clock Generation Circuit
PLL Control Register 0^{(1, 2, 5)}
b7 b6 b5 b4 b3 b2 b1 b0
101
Symbol
PLC0
Address
002616
Bit
Symbol
Bit Name
After Reset
0001 X0102
Function
RW
PLC00
RW
b2 b1 b0
0 1 1: Multiply-by-6
PLC01
Programmable Counter
Select Bit⁽³⁾
1 0 0: Multiply-by-8
Do not set to values other than the
RW
above
PLC02
RW
Reserved Bit
(b3)
Reserved Bit
(b4)
When read,
RO
its content is indeterminate
Set to "1"
RW
Reserved Bit
Set to "0"
RW
(b5)
Reserved Bit
Set to "1"
RW
(b6)
PLC07 Operation Enable Bit^{(4) 0: PLL is Off}
RW
1: PLL is On
NOTES:
1. Rewrite the PLC0 register after the PRC0 bit in the PRCR register is set to "1" (write enabled).
2. If the PM21 bit in the PM2 register is set to "1" (clock change disabled), the PLC0 register setting does
not change when written.
3. Set the PLC02 to PLC00 bits when the PLC07 bit is set to "0". Once these bits are set, they cannot be
changed.
4. Set the CM17 bit in the CM1 register to "0" (main clock as CPU clock source) and the PLC07 bit to "0"
before entering wait or stop mode.
5. Set the PLC0 and PLC1 registers simultaneously in 16-bit units.
PLL Control Register 1^{(1, 2, 3, 4)}
b7 b6 b5 b4 b3 b2 b1 b0
000 0 10
Symbol
PLC1
Address
002716
After Reset
000X 00002
Bit
Symbol
Bit Name
Function
RW
Reserved Bit
Set to "0"
RW
(b0)
Reserved Bit
Set to "1"
RW
(b1)
PLC12 ^{PLL Clock Division}
Switch Bit
0: Divide-by-2
1: Divide-by-3
RW
Reserved Bit
(b3)
(b4) ^{Reserved Bit}
Set to "0"
RW
When read,
its content is indeterminate
RO
Reserved Bit
Set to "0"
RW
(b7 - b5)
NOTES:
1. Rewrite the PLC1 register after the PRC0 bit in the PRCR register is set to "1" (write enabled).
2. If the PM21 bit in the PM2 register is set to "1" (clock change disabled), the PLC1 register does not
change when written.
3. Set the PLC1 register when the PLC07 bit is set to "0" (PLL off).
4. Set the PLC0 and PLC1 registers simultaneously in 16-bit units.
Figure 8.7 PLC0 and PLC1 Registers
Rev. 1.00 Nov. 01, 2005 Page 63 of 330
REJ09B0271-0100