M32C80 Datasheet, PDF (308/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
23. Electrical Characteristics
VCC1=VCC2=5V
Switching Characteristics
(VCC1 = VCC2 = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85^oC unless otherwise specified)
Table 23.19 Memory Expansion Mode and Microprocessor Mode
(when accessing external memory space)
Symbol
Parameter
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
th(WR-CS)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(DB-WR)
th(WR-DB)
tw(WR)
Address Output Delay Time
Address Output Hold Time (BCLK standard)
Address Output Hold Time (RD standard)
Address Output Hold Time (WR standard)
Chip-Select Signal Output Delay Time
Chip-Select Signal Output Hold Time (BCLK standard)
Chip-Select Signal Output Hold Time (RD standard)
Chip-Select Signal Output Hold Time (WR standard)
RD Signal Output Delay Time
RD Signal Output Hold Time
WR Signal Output Delay Time
WR Signal Output Hold Time
Data Output Delay Time (WR standard)
Data Output Hold Time (WR standard)
WR Output Width
Measurement
Condition
Standard
Unit
Min.
Max.
18
ns
-3
ns
0
ns
(Note 1)
ns
18
ns
-3
ns
See Figure 23.1
0
ns
(Note 1)
ns
18
ns
-5
ns
18
ns
-5
ns
(Note 2)
ns
(Note 1)
ns
(Note 2)
ns
NOTES:
1. Values can be obtained from the following equations, according to BCLK frequency.
th(WR – DB) =
10 ⁹
– 10 [ns]
f(BCLK) X 2
th(WR – AD) =
10 ⁹
– 10 ^[ns]
f(BCLK) X 2
th(WR – CS) =
10 ⁹
– 10 [ns]
f(BCLK) X 2
2. Values can be obtained from the following equations, according to BCLK frequency and external bus cycles.
tw(WR) =
td(DB – WR) =
10⁹ X n
f(BCLK) X 2
10⁹ X m
f(BCLK)
– 15
– 20
[ns] _{(if external bus cycle is aφ + bφ, n=(bx2)-1)}
[ns] _{(if external bus cycle is aφ + bφ, m= b)}
Rev. 1.00 Nov. 01, 2005 ^{Page 289} of 330
REJ09B0271-0100