M32C80 Datasheet, PDF (278/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
21. Intelligent I/O (Communication Function)
21.1.2 HDLC Data Processing Mode (Communication Units 0 and 1)
In HDLC data processing mode, bit stuffing, flag detection, abort detection and CRC calculation are available
for HDLC control. f1, f8 or f2n can be selected as the transfer clock. No pin is used.
To convert data, data to be transmitted is written to the GiTB register (i=0,1) and the data conversion result is
restored after data conversion. If any data are in the GiTO register after data conversion, the conversion is
terminated. If no data is in the GiTO register, bit stuffing processing is executed regardless of no data avail-
able in the transmit output buffer. A CRC value is calculated every time one bit is converted. If no data is in the
GiRI register, received data conversion is terminated.
Table 21.8 list specifications of the HDLC data processing mode. Tables 21.9 and 21.10 list clock settings.
Table 21.11 lists register settings.
Table 21.8 HDLC Processing Mode Specifications (Communication Units 0 and 1)
Item
Input Data Format
Output Data Format
Transfer Clock
I/O Method
Bit Stuffing
Flag Detection
Abort Detection
CRC
Data Processing Start
Condition
Specification
8-bit data fixed, bit alignment is optional
8-bit data fixed
See Tables 21.9 and 21.10
• During transmit data processing,
value set in the GiTB register is converted in HDLC data processing mode and
transferred to the GiTO register.
• During received data processing,
value set in the GiRI register is converted in HDLC data processing mode and
transferred to the GiRB register. The value in the GiRI register is also transferred to
the GiTB register (received data register).
During transmit data processing, "0" following five continuous "1" is inserted.
During received data processing, "0" following five continuous "1" is deleted.
Write the flag data "7E16" to the GiCMPj register (j=0 to 3) to use the special commu-
nication interrupt (the SRTiR bit in the IIO4IR register)
Write the masked data "0116" to the GiMSKj register
The CRC1 and CRC0 bits are set to "112" (X¹⁶+X¹²+X⁵+1).
The CRCV bit is set to "1" (set to "FFFF16").
• During transmit data processing,
CRC calculation result is stored into the GiTCRC register. The TCRCE bit in the
GiETC register is set to "1" (transmit CRC used).
The CRC calculation result is reset when the TE bit in the GiCR register is set to "0"
(transmit disabled).
• During received data processing,
CRC calculation result is stored into the GiRCRC register. The RCRCE bit in the
GiERC register is set to "1" (receive CRC used).
The CRC calculation result is reset by comparing the flag data "7E16" and matching
the result with the value in the GiCMP3 register. The ACRC bit in the GiEMR regis-
ter is set to "1" (CRC reset).
The following conditions are required to start transmit data processing:
• The TE bit in the GiCR register is set to "1" (transmit enabled)
• Data is written to the GiTB register
The following conditions are required to start receive data processing:
• The RE bit in the GiCR register is set to "1" (receive enabled)
• Data is written to the GiRI register
Rev. 1.00 Nov. 01, 2005 ^{Page 259} of 330
REJ09B0271-0100