M32C80 Datasheet, PDF (83/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
8. Clock Generation Circuit
Processor Mode Register 2⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
0 0000
0
Symbol
PM2
Address
001316
After Reset
0016
Bit
Symbol
Bit Name
Function
RW
(b0)
PM21
Reserved Bit
System Clock Protect
Bit^{(2, 3)}
WDT Count Source
PM22 _{Protect Bit}(2, 4)
Set to "0"
RW
0: Protects the clock by a PRCR
register setting
RW
1: Disables a clock change
0: Selects BCLK as count source of
the watchdog timer
1: Selects the on-chip oscillator clock
RW
as count source of the watchdog
timer
Reserved Bit
Set to "0"
RW
(b7 - b3)
NOTES:
1. Rewrite the PM2 register after the PRC1 bit in the PRCR register is set to "1" (write enabled).
2. Once the PM22 and PM21 bits are set to "1", they can not be set to "0" by program.
3. When the PM21 bit is set to "1",
the CPU clock keeps running when the WAIT instruction is executed;
nothing is changed even if following bits are set to either "0" or "1".
• the CM02 bit in the CM0 register (the peripheral function clock is not stopped in wait mode.)
• the CM05 bit in the CM0 register (the main clock is not stopped.)
• the CM07 bit in the CM0 register (a CPU clock source is not changed.)
• the CM10 bit in the CM1 register (the microcomputer does not enter stop mode.)
• the CM17 bit in the CM1 register (a CPU clock source is not changed.)
• the CM20 bit in the CM2 register (oscillation stop detect function settings are not changed.)
• all bits in the PLC0 and PLC1 registers (PLL frequency synthesizer function settings are not changed.)
4. When the PM22 bit is set to "1",
the on-chip oscillator clock becomes a count source of the watchdog timer after the on-chip oscillator starts;
write to the CM10 bit is disabled (the microcomputer does not enter stop mode.);
the watchdog timer keeps running when the microcomputer is in wait mode and hold state.
Figure 8.8 PM2 Register
Rev. 1.00 Nov. 01, 2005 Page 64 of 330
REJ09B0271-0100