M32C80 Datasheet, PDF (72/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
7. Bus
7.2.5 ALE Signal
The ALE signal latches an address of the multiplexed bus. Latch an address on the falling edge of the
ALE signal. The PM15 and PM14 bits in the PM1 register determine the output pin for the ALE signal.
The ALE signal is output to internal space and external space.
(1) 8-Bit Data Bus
ALE
D0/A0 to D7/A7
Address
Data ⁽¹⁾
(2) 16-Bit Data Bus
ALE
D0/A0 to D15/A15
Address
Data⁽¹⁾
A8 to A15
Address
A16 to A19
Address ⁽²⁾
A16 to A19
Address⁽²⁾
A20/CS3
A21/CS2
A22/CS1
A23/CS0
Address or CS
A20/CS3
A21/CS2
A22/CS1
A23/CS0
Address or CS
NOTES:
1. D0/A0 to D7/A7 are placed in high-impedance states when read.
2. When the multiplexed bus is selected for all CS areas, the address bus becomes an I/O port.
Figure 7.10 ALE Signal and Address/Data Bus
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7.2.6 RDY Signal
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The RDY signal facilitates access to external devices requiring longer access time. When a low-level ("L")
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signal is applied to the RDY pin on the falling edge of the last BCLK of the bus cycle, wait states are
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inserted into the bus cycle. When a high-level ("H") signal is applied to the RDY pin on the falling edge of
BCLK, the bus cycle starts running again.
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Table 7.6 lists microcomputer states when the RDY signal inserts wait states into the bus cycle. Figure
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7.11 shows an example of the RD signal that is extended by the RDY signal.
Table 7.6 Microcomputer States in Wait State⁽¹⁾
Item
State
Oscillation
On
RD Signal, WR Signal, Address Bus, Data Bus, Maintains the same state as when RDY
CS, ALE Signal, HLDA, Programmable I/O Ports signal was received
Internal Peripheral Circuits
On
NOTE:
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1. The RDY signal cannot be accepted immediately before software wait states are inserted.
Rev. 1.00 Nov. 01, 2005 Page 53 of 330
REJ09B0271-0100