M32C80 Datasheet, PDF (115/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
10. Interrupts
10.6.6 Saving a Register
In the interrupt sequence, the FLG register and PC are saved to the stack.
After the FLG register is saved to the stack, 16 high-order bits and 16 low-order bits of PC, extended to 32
bits, are saved to the stack. Figure 10.7 shows stack states before and after an interrupt request is
acknowledged.
Other important registers are saved by program at the beginning of an interrupt routine. The PUSHM
instruction can save several registers⁽¹⁾ in the register bank used.
Refer to 10.4 High-Speed Interrupt for the high-speed interrupt.
NOTE:
1. Can be selected from the R0, R1, R2, R3, A0, A1, SB and FB registers.
Address
The Stack
MSB
LSB
Address _MSB ^{The Stack}
LSB
m-6
m-5
m–4
m–3
m–2
m–1
m
m+1
Content of
previous stack
Content of
previous stack
[SP]
SP value before
an interrupt is
generated
m-6
m-5
m–4
m–3
m–2
m–1
m
m+1
PCL
PCM
PCH
0016
FLGL
FLGH
Content of
previous stack
Content of
previous stack
[SP]
New SP value
Stack state before an interrupt request is acknowledged
Stack state after an interrupt request is acknowledged
Figure 10.7 Stack States
10.6.7 Restoration from Interrupt Routine
When the REIT instruction is executed at the end of an interrupt routine, the FLG register and PC before the
interrupt sequence is performed, which have been saved to the stack, are automatically restored. The pro-
gram, executed before an interrupt request was acknowledged, starts running again. Refer to 10.4 High-
Speed Interrupt for the high-speed interrupt.
Restore registers saved by program in an interrupt routine by the POPM instruction or others before the
REIT and FREIT instructions. Register bank is switched back to the bank used prior to the interrupt
sequence by the REIT or FREIT instruction.
Rev. 1.00 Nov. 01, 2005 Page 96 of 330
REJ09B0271-0100