M32C80 Datasheet, PDF (233/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
16. Serial I/O (Special Function)
16.7 Special Mode 5 (SIM Mode)
In SIM mode, SIM interface devices can communicate in UART mode. Both direct and inverse formats are
available and a low-level ("L") signal output can be provided from the TxDi pin (i=0 to 4) when a parity error
is detected.
Table 16.34 lists specifications of SIM mode. Table 16.35 lists register settings. Tables 16.36 to 16.38 list
pin settings.
Table 16.34 SIM Mode Specifications
Item
Specification
Transfer Data Format
• Transfer data: 8-bit UART mode
• In direct format
Parity:
Even
• One stop bit
• In inverse format
Parity:
Odd
Data logic:
Direct
Transfer format: LSB first
Data logic:
Transfer format:
Inverse
MSB first
Transfer Clock
• The CKDIR bit in the UiMR register (i=0 to 4) is "0" (internal clock selected):
fj/16(m+1)⁽¹⁾ fj = f1, f8, f2n(2) m : setting value of the UiBRG register, 0016 to FF16
Do not set the CKDIR bit to "1" (external clock selected)
_______ _______
Transmit/Receive Control The CRD bit in the UiC0 register is set to "1" (CTS, RTS function disabled)
Other Setting Items
The UiIRS bit in the UiC1 register is set to "1" (transmission completed)
Transmit Start Condition To start transmitting, the following requirements must be met:
- Set the TE bit in the UiC1 register to "1" (transmit enabled)
- Set the TI bit in the UiC1 register to "0" (data in the UiTB register)
Receive Start Condition To start receiving, the following requirements must be met:
- Set the RE bit in the UiC1 register to "1" (receive enabled)
- Detect the start bit
Interrupt Request
Generation Timing
• While transmitting,
-The UiIRS bit is set to "1" (transmission completed):
when data transmission from the UARTi transfer register is completed
• While receiving,
Error Detection
when data is transferred from the UARTi receive register to the UiRB register (reception completed)
• Overrun error⁽¹⁾
This error occurs when the eighth bit of the next data is received before reading the
UiRB register
• Framing error
This error occurs when the number of the stop bit set is not detected
• Parity error
This error occurs when the number of "1" in parity bit and character bits differs from
the number set
• Error sum flag
The SUM bit is set to "1" when an overrun error, framing error or parity error occurs
NOTES:
1. If an overrun error occurs, the UiRB register is indeterminate. The IR bit setting in the SiRIC register does not
change to "1" (interrupt requested).
2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Rev. 1.00 Nov. 01, 2005 Page 214 of 330
REJ09B0271-0100