M32C80 Datasheet, PDF (238/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
16. Serial I/O (Special Function)
16.7.2 Format
16.7.2.1 Direct Format
Set the PRYE bit in the UiMR register (i=0 to 4) to "1" (parity enabled), the PRY bit to "1" (even
parity), the UFORM bit in the UiC0 register to "0" (LSB first) and the UiLCH bit in the UiC1 register to
"0" (not inversed). When data are transmitted, data set in the UiTB register are transmitted with the
even-numbered parity, starting from D0. When data are received, received data are stored in the
UiRB register, starting from D0. The even-numbered parity determines whether a parity error occurs.
16.7.2.2 Inverse Format
Set the PRYE bit to "1", the PRY bit to "0" (odd parity), the UFORM bit to "1" (MSB first) and the
UiLCH bit to "1" (inversed). When data are transmitted, values set in the UiTB register are logically
inversed and are transmitted with the odd-numbered parity, starting from D7. When data are re-
ceived, received data are logically inversed to be stored in the UiRB register, starting from D7. The
odd-numbered parity determines whether a parity error occurs.
(1) Direct Format
Transfer Clock ^"H"
"L"
TxDi ^"H"
"L"
(2) Inverse Format
Transfer Clock ^"H"
"L"
TxDi ^"H"
"L"
i=0 to 4
D0 D1 D2 D3 D4 D5 D6 D7 P
P: Even parity
D7 D6 D5 D4 D3 D2 D1 D0 P
P: Odd parity
Figure 16.32 SIM Interface Format
Rev. 1.00 Nov. 01, 2005 Page 219 of 330
REJ09B0271-0100