M32C80 Datasheet, PDF (153/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
14. Timer (Timer A)
Trigger Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRGSR
Address
034316
After Reset
0016
Bit
Symbol
Bit Name
Function
RW
b1 b0
TA1TGL
0 0: Selects an input to the TA1IN pin ^RW
Timer A1 Event/Trigger _{0 1: Selects the TB2 overflows(1)}
Select Bit
TA1TGH
1 0: Selects the TA0 overflows⁽¹⁾
RW
1 1: Selects the TA2 overflows⁽¹⁾
b3 b2
TA2TGL
0 0: Selects an input to the TA2IN pin RW
Timer A2 Event/Trigger _{0 1: Selects the TB2 overflows}(1)
Select Bit
TA2TGH
1 0: Selects the TA1 overflows⁽¹⁾
1 1: Selects the TA3 overflows⁽¹⁾
RW
b5 b4
TA3TGL
0 0: Selects an input to the TA3IN pin RW
Timer A3 Event/Trigger _{0 1: Selects the TB2 overflows}(1)
Select Bit
TA3TGH
1 0: Selects the TA2 overflows⁽¹⁾
1 1: Selects the TA4 overflows⁽¹⁾
RW
b7 b6
TA4TGL
0 0: Selects an input to the TA4IN pin RW
Timer A4 Event/Trigger
Select Bit
TA4TGH
0 1: Selects the TB2 overflows⁽¹⁾
1 0: Selects the TA3 overflows⁽¹⁾
RW
1 1: Selects the TA0 overflows⁽¹⁾
NOTE:
1. Overflow or underflow
Count Source Prescaler Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TCSPR
Address
035F16
Bit
Symbol
Bit Name
CNT0
After Reset⁽²⁾
0XXX 00002
Function
RW
RW
CNT1
If setting value is n, f2n is the
Divide Ratio Select Bit⁽¹⁾
main clock, on-chip oscillator or
PLL clock divided by 2n.
RW
CNT2
Not divided if n=0.
RW
CNT3
RW
(b6 - b4) ^{Reserved Bit}
When read,
its content is indeterminate
RO
0: Stops a divider
CST Operation Enable Bit
1: Starts a divider
RW
NOTES:
1. Set the CST bit to "0" before the CNT3 to CNT0 bits are rewritten.
2. The TCSPR register maintains values set before reset, even after software reset or watchdog timer
reset has performed.
Figure 14.7 TRGSR Register and TCSPR Register
Rev. 1.00 Nov. 01, 2005 Page 134 of 330
REJ09B0271-0100