M32C80 Datasheet, PDF (189/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
16. Serial I/O
UARTi Bit Rate Register (i=0 to 4)(1, ^{2, 3)}
b7
b0
Symbol
Address
After Reset
U0BRG to U4BRG 036916, 02E916, 033916, 032916, 02F916 Indeterminate
Function
Setting Range RW
If the setting value is m, the UiBRG register
divides a count source by m+1
0016 to FF16
WO
NOTES:
1. Use the MOV instruction to set the UiBRG register.
2. Set the UiBRG register while no data transfer occurs.
3. Set the CLK1 and CLK0 bits in the UiC0 register, and then the UiBRG register.
UARTi Transmit/Receive Mode Register (i=0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U0MR to U4MR
Address
036816, 02E816, 033816, 032816, 02F816
After Reset
0016
Bit
Symbol
SMD0
SMD1
SMD2
Bit Name
Function
RW
b2 b1 b0
0 0 0: Serial I/O disabled
RW
0 0 1: Clock synchronous serial I/O mode
Serial I/O Mode Select ^{0 1 0: I2C mode}
Bit
1 0 0: UART mode, 7-bit transfer data
RW
1 0 1: UART mode, 8-bit transfer data
1 1 0: UART mode, 9-bit transfer data
Do not set value other than the above
RW
CKDIR
Internal/External Clock 0: Internal clock
Select Bit
1: External clock
RW
STPS
Stop Bit Length Select 0: 1 stop bit
Bit
1: 2 stop bits
RW
PRY
Odd/Even Parity Select
Enables when PRYE = 1
0: Odd parity
RW
Bit
1: Even parity
PRYE Parity Enable Bit
0: Disables a parity
RW
1: Enables a parity
IOPOL
TxD,RxD Input/Output 0: Not inversed
Polarity Switch Bit
1: Inverse
RW
Figure 16.3 U0BRG to U4BRG Registers and U0MR to U4MR Registers
Rev. 1.00 Nov. 01, 2005 Page 170 of 330
REJ09B0271-0100