M32C80 Datasheet, PDF (239/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
17. A/D Converter
17. A/D Converter
The A/D converter consists of one 10-bit successive approximation A/D converter with a capacitive cou-
pling amplifier.
The result of an A/D conversion is stored into the A/D registers corresponding to selected pins. It is stored
into the AD00 register only when DMAC operating mode is entered.
Table 17.1 lists specifications of the A/D converter. Figure 17.1 shows a block diagram of the
A/D converter. Figures 17.2 to 17.6 show registers associated with the A/D converter.
Table 17.1 A/D Converter Specifications
Item
Specification
A/D Conversion Method
Analog Input Voltage⁽¹⁾
Operating Clock, ØAD(2)
Successive approximation (with a capacitive coupling amplifier)
0V to AVCC (VCC1)
fAD, fAD/2, fAD/3, fAD/4, fAD/6, fAD/8
Resolution
8 bits or 10 bits
Operating Mode
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,
Analog Input Pins⁽³⁾
repeat sweep mode 1
10 pins
8 pins for AN0 to AN7
2 extended input pins (ANEX0 and ANEX1)
A/D Conversion Start Condition • Software trigger
The ADST bit in the AD0CON0 register is set to "1" (A/D conversion started) by
program
• External trigger (re-trigger is enabled)
__________
When a falling edge is applied to the ADTRG pin after the ADST bit is set to "1" by
program
• Hardware trigger (re-trigger is enabled)
The timer B2 interrupt request of the three-phase motor control timer functions
(after the ICTB2 counter completes counting) is generated after the ADST bit is
set to "1" by program
Conversion Rate Per Pin
• Without the sample and hold function
8-bit resolution : 49 ØAD cycles
10-bit resolution : 59 ØAD cycles
• With the sample and hold function
8-bit resolution : 28 ØAD cycles
10-bit resolution : 33 ØAD cycles
NOTES:
1. Analog input voltage is not affected by the sample and hold function status.
2. ØAD frequency must be under 16 MHz when VCC1=5V.
ØAD frequency must be under 10 MHz when VCC1=3.3V.
Without the sample and hold function, the ØAD frequency is 250 kHz or more.
With the sample and hold function, the ØAD frequency is 1 MHz or more.
3. AVCC=VREF=VCC1, A/D input voltage (for AN0 to AN7, ANEX0, and ANEX1) ≤ VCC1.
Rev. 1.00 Nov. 01, 2005 ^{Page 220} of 330
REJ09B0271-0100