M32C80 Datasheet, PDF (199/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
16. Serial I/O (Clock Synchronous Serial I/O)
(1) Transmit Timing (Internal clock selected)
Tc
Transfer Clock
TE bit in the UiC1 ^"1"
register
"0"
TI bit in the UiC1 ^"1"
register
"0"
"H"
CTSi
"L"
CLKi
Data is set in the UiTB register
Data is transferred from the UiTB register to the UARTi transmit register
TCLK
Pulse stops because an "H"
signal is applied to CTSi
Pulse stops because the TE bit is set to "0"
TxDi
TXEPT bit in
"1"
the UiC0 register
"0"
IR bit in the SiTIC "1"
register
"0"
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
Set to "0" by an interrupt request acknowledgement or by program
The above applies under the following conditions:
TC=TCLK=2(m+1)/fj
• The CKDIR bit in the UiMR register is set to "0" (internal clock selected)
• The CRD bit in the UiC0 register is set to "0" (RTS/CTS function enabled)
The CRS bit is set to "0" (CTS function selected)
• The CKPOL bit the in UiC0 register is set to "0" (data transmitted on the
falling edge of the transfer clock)
• The UiIRS bit in the UiC1 register is set to "0" (no data in the UiTB register)
fj: Count source frequency set in the UiBRG register (f1, f8, f2n(1))
m: Setting value of the UiBRG register
i = 0 to 4
NOTE:
1. The CNT3 to CNT0 bits in the TCSPR register select no division (
n=0) or divide-by-2n (n=1 to 15).
(2) Receive Timing (External clock selected)
RE bit in the UiC1 ^"1"
register
"0"
TE bit in the UiC1 ^"1"
register
"0"
Dummy data is set in the UiTB register
TI bit in the UiC1 ^"1"
register
"0"
"H"
RTSi
"L"
CLKi
Data is transferred from the UiTB register to the UARTi transmit register
1 / fEXT
An "L" signal is applied when
the UiRB register is read
Received data is taken in
RxDi
D0 D¹ D² D3 D⁴ D⁵ D⁶ D7
D0 D¹ D² D³ D⁴ D⁵ D6 D⁷ D⁰ D1 D2 D³ D4 D5 D6
RI bit in the UiC1
register
Date is transferred from the UARTi
"1" receive register to the UiRB register
"0"
Read by the UiRB register
IR bit in the SiRIC "1"
register
"0"
OER bit in the
"1"
UiRB register
"0"
Set to "0" by an interrupt request acknowledgement or by program
The above applies under the following conditions:
• The CKDIR bit in the UiMR register is set to "1" (external clock selected)
• The CRD bit in the UiC0 register is set to "0" (RTS/CTS function enabled)
The CRS bit is set to "1" (RTS function selected)
• The CKPOL bit in the UiC0 register is set to "0"
(Data is received on the rising edge of the transfer clock)
fEXT: External clock frequency i=0 to 4
Meet the following conditions while an "H" signal is applied to
the CLKi pin before receiving data:
• Set the TE bit in the UiC1 register to "1" (transmit enable)
• Set the RE bit in the UiC1 register to "1" (receive enable)
• Write dummy data to the UiTB register
Figure 16.10 Transmit and Receive Operation
Rev. 1.00 Nov. 01, 2005 ^{Page 180} of 330
REJ09B0271-0100