M32C80 Datasheet, PDF (317/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
23. Electrical Characteristics
VCC1=VCC2=3.3V
Timing Requirements
(VCC1=VCC2= 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85^oC unless otherwise specified)
Table 23.24 External Clock Input
Symbol
Parameter
tc
tw(H)
tw(L)
tr
tf
External Clock Input Cycle Time
External Clock Input High ("H") Width
External Clock Input Low ("L") Width
External Clock Rise Time
External Clock Fall Time
Standard
Unit
Min.
Max.
41
ns
18
ns
18
ns
5
ns
5
ns
Table 23.25 Memory Expansion Mode and Microprocessor Mode
Symbol
Parameter
Standard
Unit
Min. Max.
tac1(RD-DB) Data Input Access Time (RD standard)
(Note 1) ns
tac1(AD-DB) Data Input Access Time (AD standard, CS standard)
(Note 1) ns
tac2(RD-DB) Data Input Access Time (RD standard, when accessing a space with the multiplexed bus)
(Note 1) ns
tac2(AD-DB) Data Input Access Time (AD standard, when accessing a space with the multiplexed bus)
(Note 1) ns
tsu(DB-BCLK) Data Input Setup Time
30
ns
tsu(RDY-BCLK) RDY Input Setup Time
40
ns
tsu(HOLD-BCLK) HOLD Input Setup Time
60
ns
th(RD-DB)
Data Input Hold Time
0
ns
th(BCLK-RDY) RDY Input Hold Time
0
ns
th(BCLK-HOLD) HOLD Input Hold Time
0
ns
td(BCLK-HLDA) HLDA Output Delay Time
25 ns
NOTE:
1. Values can be obtained from the following equations, according to BCLK frequecncy and external bus cycles. Insert a
wait state or lower the operation frequency, f(BCLK), if the calculated value is negative.
10⁹ X m
tac1(RD – DB) = _{f(BCLK) X 2} – 35
tac1(AD – DB) =
10⁹ X n
f(BCLK)
– 35
10⁹ X m
tac2(RD – DB) = _{f(BCLK) X 2} – 35
10⁹ X p
tac2(AD – DB) = _{f(BCLK) X 2} – 35
[ns] (if external bus cycle is aφ + bφ, m=(bx2)+1)
[ns] (if external bus cycle is aφ + bφ, n=a+b)
[ns] (if external bus cycle is aφ + bφ, m=(bx2)-1)
[ns] (if external bus cycle is aφ + bφ, p={(a+b-1)x2}+1)
Rev. 1.00 Nov. 01, 2005 ^{Page 298} of 330
REJ09B0271-0100