M32C80 Datasheet, PDF (166/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
14. Timer (Timer B)
14.2 Timer B
Figure 14.16 shows a block diagram of the timer B. Figures 14.17 to 14.19 show registers associated with
the timer B. The timer B supports the following three modes. The TMOD1 and TMOD0 bits in the TBiMR
register (i=0 to 5) determine which mode is used.
• Timer mode : The timer counts an internal count source.
• Event counter mode : The timer counts pulses from an external source or overflow and underflow of
another timer.
• Pulse period/pulse width measurement mode : The timer measures pulse period or pulse width of an
external signal.
Table 14.8 lists TBiIN pin settings.
High-order Bits of Data Bus
Select Clock Source
TCK1 and
TCK0
f1 ⁰⁰
f8 ⁰¹
00:
01:
Timer
Pulse
Mode
Period/Pulse
Width
TMOD1
TMOD0
and
Measurement Mode
f2n^{(1) 10}
fc32 ¹¹
TBj Overflow
Signal^(2,3)
1
TCK1
01: Event
Counter Mode
TBiIN
Polarity Switching ⁰
and Edge Pulse
Low-order Bits of Data Bus
8 low-order
bits
Reload Register
TBiS
Counter
Counter Reset Circuit
i=0 to 5
NOTES:
1. The CNT3 to CNT0 bits in the TCSPR register select no
division (n=0) or divide-by-2n (n=1 to 15).
2. Overflow signal or underflow signal.
3. j=i-1, except j=2 when i=0 j=5 when i=3
TCK1 and TCK0, TMOD1 and TMOD0: Bits in the TBiMR Register
TBiS: Bits in the TABSR and the TBSR Register
TBi
Timer B0
Timer B1
Timer B2
Timer B3
Timer B4
Timer B5
Address
035116 035016
035316 035216
035516 035416
031116 031016
031316 031216
031516 031416
TBj
Timer B2
Timer B0
Timer B1
Timer B5
Timer B3
Timer B4
8 high-
order
bits
Figure 14.16 Timer B Block Diagram
Timer Bi Register⁽¹⁾ (i=0 to 5)
b15
b8 b7
b0 Symbol
Address
After Reset
TB0 to TB2 035116 - 035016, 035316 - 035216, 035516 - 035416 Indeterminate
TB3 to TB5 031116 - 031016, 031316 - 031216, 031516 - 031416 Indeterminate
Mode
Function
Setting Range RW
Timer Mode
If setting value is n, a count source _{000016 to FFFF16 RW}
is divided by n+1
Event Counter
Mode
If setting value is n, a count source
is divided by n+1⁽²⁾
000016 to FFFF16
RW
Pulse Period/Pulse ^{A count source is incremented}
Width Measurement between one valid edge and
RO
Mode
another valid edge of TBiIN pulse
NOTES:
1. Use 16-bit data for reading and writing.
2. The TBi register counts how many pulse inputs are provided externally or how many times another
timer counter overflows and underflows.
Figure 14.17 TB0 to TB5 Registers
Rev. 1.00 Nov. 01, 2005 Page 147 of 330
REJ09B0271-0100