M32C80 Datasheet, PDF (124/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
11. Watchdog Timer
11. Watchdog Timer
The watchdog timer monitors the program executions and detects defective program. It allows the micro-
computer to trigger a reset or to generate an interrupt if the program error occurs. The watchdog timer
contains a 15-bit counter, which is decremented by the CPU clock that the prescaler divides. The CM06 bit
in the CM0 register determines whether a watchdog timer interrupt request or reset is generated if the
watchdog timer underflows. Once the CM06 bit is set to "1", it cannot be changed to "0" ( watchdog timer
interrupt) by program. The CM06 bit is set to "0" only after reset.
When the main clock, on-chip oscillator clock, or PLL clock runs as the CPU clock, the WDC7 bit in the
WDC register determine whether the prescaler divides the clock by 16 or by 128. When the sub clock runs
as the CPU clock, the prescaler divides the clock by 2 regardless of the WDC7 bit setting. Watchdog timer
cycle is calculated as follows. Marginal errors, due to the prescaler, may occur in watchdog timer cycle.
When the main clock, on-chip oscillator clock, or PLL clock is selected as the CPU clock,
Divide-by-16 or -128 prescaler x counter value of watchdog timer (32768)
Watchdog timer cycle =
CPU clock
When the sub clock is selected as the CPU clock,
Divide-by-2 prescaler x counter value of watchdog timer (32768)
Watchdog timer cycle =
CPU clock
For example, if the CPU clock frequency is 30MHz and the prescaler divides it by 16, the watchdog timer
cycle is approximately 17.5 ms.
The watchdog timer is reset when the WDTS register is set and when a watchdog timer interrupt request is
generated. The prescaler is reset only when the microcomputer is reset. Both watchdog timer and prescaler
stop after reset. They begin counting when the WDTS register is set.
The watchdog timer and prescaler stop in stop mode, wait mode and hold state. They resume counting
from the value held when the mode or state is exited.
Figure 11.1 shows a block diagram of the watchdog timer. Figure 11.2 shows registers associated with the
watchdog timer.
CPU Clock
HOLD Signal
Write to WDTS Register
Internal Reset Signal
Prescaler
1/16
CM07 = 0
WDC7 = 0
1/128
CM07 = 0
WDC7 = 1
CM07 = 1
1/2
PM22 = 0
On-chip Oscillator Clock
PM22 = 1
Watchdog Timer
Set to
7FFF16
CM06, CM07: Bits in the CM0 Register
WDC7: Bit in the WDC Register
PM22: Bit in the PM2 Register
Figure 11.1 Watchdog Timer Block Diagram
Rev. 1.00 Nov. 01, 2005 Page 105 of 330
REJ09B0271-0100
CM06 = 0
Watchdog Timer
Interrupt Request
Reset
CM06 = 1