M32C80 Datasheet, PDF (270/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
21. Intelligent I/O (Communication Function)
SI/O Expansion Receive Control Register i (i=0,1)(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
G0ERC, G1ERC
Address
00FD16, 013D16
After Reset
0016
Bit
Symbol
Bit Name
Data Compare
CMP0E Function 0
Select Bit
Data Compare
CMP1E Function 1
Select Bit
Data Compare
CMP2E Function 2
Select Bit
Data Compare
CMP3E Function 3
Select Bit
Function
RW
0: The GiDR register (receive data register) is
not compared with the GiCMP0 register
1: The GiDR register is compared with the
RW
GiCMP0 register
0: The GiDR register (receive data register) is
not compared with the GiCMP1 register
1: The GiDR register is compared with the
RW
GiCMP1 register
0: The GiDR register (receive data register) is
not compared with the GiCMP2 register
1: The GiDR register is compared with the
RW
GiCMP2 register
0: The GiDR register (receive data register) is
not compared with the GiCMP3 register
1: The GiDR register is compared with the
RW
GiCMP3 register⁽²⁾
RCRCE
Receive CRC
Enable Bit
0: Not used
1: Used
RW
Receive Shift
0: Receive shift operation disabled
RSHTE Operation
Enable Bit
1: Receive shift operation enabled
RW
RBSF0
Receive Bit
Stuffing "1" Delete
Select Bit
0: "1" is not deleted
1: "1" is deleted
RW
RBSF1
Receive Bit
Stuffing "0" Delete
Select Bit
0: "0" is not deleted
1: "0" is deleted
RW
NOTES:
1. The GiERC register is used in HDLC data processing mode.
Set to "0010 00002" in clock synchronous serial I/O mode.
2. Set the CMP3E bit to "1" to set the ACRC bit in the GiEMR register to "1" (CRC reset function used).
Figure 21.7 G0ERC and G1ERC Registers
Rev. 1.00 Nov. 01, 2005 ^{Page 251} of 330
REJ09B0271-0100