M32C80 Datasheet, PDF (128/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
12. DMAC
12. DMAC
This microcomputer contains four DMAC (direct memory access controller) channels that allow data to be
sent to memory without using the CPU. DMAC transmits a 8- or 16-bit data from a source address to a
destination address whenever a transmit request occurs. DMA0 and DMA1 must be prioritized if using
DMAC. DMA2 and DMA3 share registers required for high-speed interrupts. High-speed interrupts cannot
be used when using three or more DMAC channels.
The CPU and DMAC use the same data bus, but DMAC has a higher bus access privilege than the CPU.
The cycle-steal method employed on DMAC enables high-speed operation between a transfer request and
the complete transmission of 16-bit (word) or 8-bit (byte) data. Figure 12.1 shows a mapping of registers to
be used for DMAC. Table 12.1 lists specifications of DMAC. Figures 12.2 to 12.5 show registers associ-
ated with DMAC.
Because the registers shown in Figure 12.1 are allocated in the CPU, use the LDC instruction to write to the
registers. To set the DCT2, DCT3, DRC2, DRC3, DMA2 and DMA3 registers, set the B flag to "1" (register
bank 1) and set the R0 to R3, A0, A1 registers with the MOV instruction.
To set the DSA2 and DSA3 registers, set the B flag to "1" and set the SB and FB registers with the LDC
instruction. To set the DRA2 and DRA3 registers, set the SVP and VCT registers with the LDC instruction.
DMAC-associated Registers
DMD0
DMD1
DCT0
DCT1
DRC0
DRC1
DMA0
DMA1
DSA0
DSA1
DRA0
DRA1
DMA Mode Register 0
DMA Mode Register 1
DMA 0 Transfer Count Register
DMA 1 Transfer Count Register
DMA 0 Transfer Count Reload Register⁽¹⁾
DMA 1 Transfer Count Reload Register⁽¹⁾
DMA 0 Memory Address Register
DMA 1 Memory Address Register
DMA 0 SFR Address Register
DMA 1 SFR Address Register
DMA 0 Memory Address Reload Register⁽¹⁾
DMA 1 Memory Address Reload Register⁽¹⁾
When Three or More DMAC Channels are Used,
the Register Bank 1 is Used as DMAC Registers
DCT2 (R0)
DCT3 (R1)
DRC2 (R2)
DRC3 (R3)
DMA2 (A0)
DMA3 (A1)
DSA2 (SB)
DSA3 (FB)
DMA2 Transfer Count Register
DMA3 Transfer Count Register
DMA2 Transfer Count Reload Register⁽¹⁾
DMA3 Transfer Count Reload Register⁽¹⁾
DMA2 Memory Address Register
DMA3 Memory Address Register
DMA2 SFR Address Register
DMA3 SFR Address Register
When Three or More DMAC Channels are Used,
the High-speed Interrupt Register is Used as DMAC
Registers
SVF
Flag Save Register
DRA2 (SVP)
DMA2 Memory Address Reload Register⁽¹⁾
DRA1 (VCT)
DMA3 Memory Address Reload Register⁽¹⁾
When using DMA2 and DMA3, use the CPU registers shown in parentheses ().
NOTE:
1. Registers are used for repeat transfer, not for single transfer.
Figure 12.1 Register Mapping for DMAC
Rev. 1.00 Nov. 01, 2005 Page 109 of 330
REJ09B0271-0100