M32C80 Datasheet, PDF (339/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
24. Precautions (Timer)
24.8.3 Timer B
24.8.3.1 Timer B (Timer Mode, Event Counter Mode)
• The TBiS (i=0 to 5) bit is set to "0" (stops counting) after reset. Set the TBiS bit to "1" (starts
counting) after selecting an operating mode and setting TBi register.
The TB2S to TB0S bits are bits 7 to 5 in the TABSR register. The TB5S to TB3S bits are bits 7 to 5
in the TBSR register.
• The TBi register indicates the counter value during counting at any given time. However, the
counter is "FFFF16" when reloading. The setting value can be read after setting the TBi register
while the counter stops and before the counter starts counting.
24.8.3.2 Timer B (Pulse Period/Pulse Width Measurement Mode)
• The IR bit in the TBiIC (i=0 to 5) register is set to "1" (interrupt requested) when the valid edge of a
pulse to be measured is input and when the timer Bi counter overflows. The MR3 bit in the TBiMR
register determines the interrupt source within an interrupt routine.
• Use another timer to count how often the timer counter overflows when an interrupt source cannot
be determined by the MR3 bit, such as when a pulse to be measured is input at the same time the
timer counter overflows.
• To set the MR3 bit in the TBiMR register to "0" (no overflow), set the TBiMR register after the MR3
bit is set to "1" (overflow) and one or more cycles of the count source are counted, while the TBiS
bits in the TABSR and TBSR registers are set to "1" (starts counting).
• The IR bit in the TBiIC register is used to detect overflow only. Use the MR3 bit only to determine
interrupt source within an interrupt routine.
• Indeterminate values are transferred to the reload register during the first valid edge input after
counting is started. Timer Bi interrupt request is not generated at this time.
• The counter value is indeterminate when counting is started. Therefore, the MR3 bit setting may
change to "1" (overflow) and causes timer Bi interrupt requests to be generated until a valid edge is
input after counting is started.
• The IR bit may be set to "1" (interrupt requested) if the MR1 and MR0 bits in the TBiMR register are
set to a different value after a count begins. If the MR1 and MR0 bits are rewritten, but to the same
value as before, the IR bit remains unchanged.
• Pulse width measurement measures pulse width continuously. Use program to determine whether
measurement results are high ("H") or low ("L").
Rev. 1.00 Nov. 01, 2005 ^{Page 320} of 330
REJ09B0271-0100