M32C80 Datasheet, PDF (108/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
10. Interrupts
10.6 Interrupt Request Acknowledgement
Software interrupts and special interrupts occur when conditions to generate an interrupt are met.
The peripheral function interrupts are acknowledged when all conditions below are met.
• I flag
= "1"
• IR bit
= "1"
• ILVL2 to ILVL0 bits
> IPL
The I flag, IPL, IR bit and ILVL2 to ILVL0 bits are independent of each other. The I flag and IPL are in the
FLG register. The IR bit and ILVL2 to ILVL0 bits are in the interrupt control register.
10.6.1 I Flag and IPL
The I flag enables or disables maskable interrupts. When the I flag is set to "1" (enable), all maskable
interrupts are enabled; when the I flag is set to "0" (disable), they are disabled. The I flag is automatically
set to "0" after reset.
IPL, consisting of three bits, indicates the interrupt priority level from level 0 to level 7.
If a requested interrupt has higher priority level than indicated by IPL, the interrupt is acknowledged.
Table 10.3 lists interrupt priority levels associated with IPL.
Table 10.3 Interrupt Priority Levels
IPL2
IPL1
IPL0
Interrupt Priority Levels
0
0
0
Level 1 and above
0
0
1
Level 2 and above
0
1
0
Level 3 and above
0
1
1
Level 4 and above
1
0
0
Level 5 and above
1
0
1
Level 6 and above
1
1
0
Level 7 and above
1
1
1
All maskable interrupts are disabled
10.6.2 Interrupt Control Register and RLVL Register
The peripheral function interrupts use interrupt control registers to control each interrupt. Figures 10.3
and 10.4 show the interrupt control register. Figure 10.5 shows the RLVL register.
Rev. 1.00 Nov. 01, 2005 Page 89 of 330
REJ09B0271-0100