M32C80 Datasheet, PDF (60/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
7. Bus
Table 7.2 Processor Mode and Port Function
Processor Single-
Mode Chip Mode
Memory Expansion Mode/ Microprocessor Mode
Memory Expansion Mode
PM05 to
PM04 Bits in
PM0 Register
Data Bus Width
P00 to P07
I/O port
"012", "102"
Access CS1 or CS2 using
the Multiplexed Bus
Access All Other CS Areas using
the Separate Bus
"002"
Access all CS Areas using
the Separate Bus
"112"⁽¹⁾
Access all CS Areas using
the Multiplexed Bus
Access all
Access one or more Access all
Access one or more
Access all Access one or more
external space with external space with external space with external space with external space with external space with
8-bit data bus
16-bit data bus
8-bit data bus
16-bit data bus
8-bit data bus
16-bit data bus
Data bus
D0 to D7
Data bus
D0 to D7
Data bus
D0 to D7
Data bus
D0 to D7
I/O port
I/O port
P10 to P17
P20 to P27
P30 to P37
P40 to P43
I/O port
I/O port
I/O port
I/O port
I/O port
Address bus
Data bus⁽²⁾
A0/D0 to A7/D7
Address bus
A8 to A15
Address bus
A16 to A19
Data bus
D8 to D15
Address bus
Data bus⁽²⁾
A0/D0 to A7/D7
Address bus/
Data bus⁽²⁾
A8/D8 to A15/D15
Address bus
A16 to A19
I/O port
Address bus
A0 to A7
Address bus
A8 to A15
Address bus
A16 to A19
Data bus
D8 to D15
Address bus
A0 to A7
Address bus
A8 to A15
Address bus
A16 to A19
I/O port
I/O port
Address bus
Data bus
A0/D0 to A7/D7
Address bus
A8 to A15
Address bus
Data bus
A0/D0 to A7/D7
Address bus/
Data bus
A8/D8 to A15/D15
I/O port
I/O port
P44 to P46
P47
P50 to P53
I/O port
I/O port
I/O port
CS (Chip-select signal) or Address bus (A20 to A22)
(Refer to 7.2 Bus Control for details)⁽⁴⁾
CS (Chip-select signal) or Address bus (A23)
(Refer to 7.2 Bus Control for details)⁽⁴⁾
Outputs RD, WRL, WRH and BCLK or outputs RD, BHE, WR and BCLK
(Refer to 7.2 Bus Control for details)⁽³⁾
P54
I/O port
HDLA ⁽³⁾
HDLA ⁽³⁾
HDLA ⁽³⁾
HDLA ⁽³⁾
HDLA ⁽³⁾
HDLA ⁽³⁾
P55
I/O port
HOLD
HOLD
HOLD
HOLD
HOLD
HOLD
P56
I/O port
ALE ⁽³⁾
ALE ⁽³⁾
ALE ⁽³⁾
ALE ⁽³⁾
ALE ⁽³⁾
ALE ⁽³⁾
P57
I/O port
RDY
RDY
RDY
RDY
RDY
RDY
NOTES:
1. The PM05 and PM04 bits cannot be set to "112" (access all CS areas using multiplexed bus) in microprocessor mode
because the microcomputer starts operation using the separate bus after reset.
When the PM05 and PM04 bits are set to "112" in memory expansion mode, the microcomputer accesses 64-Kbyte
memory space per chip-select using the address bus .
2. These ports become address buses when accessing space using the separate bus.
3. The PM15 and PM14 bits in the PM1 register determines which pin outputs the ALE signal. The PM02 bit in the PM0
register selects either "WRL,WRH" or "BHE,WR" combination.
P56 provides an indeterminate output when the PM15 and PM14 bits to "002" (no ALE). It cannot be used as an I/O port.
4. The PM11 and PM10 bits in the PM1 register determine the CS signal and address bus.
Rev. 1.00 Nov. 01, 2005 Page 41 of 330
REJ09B0271-0100