M32C80 Datasheet, PDF (273/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
21. Intelligent I/O (Communication Function)
Data Compare Register ij (i=0,1, j=0 to 3)
b7
b0
Symbol
Address
After Reset
G0CMP0 to G0CMP3 00F016, 00F116, 00F216, 00F316 Indeterminate
G1CMP0 to G1CMP3 013016, 013116, 013216, 013316 Indeterminate
Function
Setting Range RW
Data to be compared
NOTE:
1. Set the GiMSK0 register to use the GiCMP0 register.
Set the GiMSK1 register to use the GiCMP1 register.
0016 to FF16
RW
Data Mask Register ij (i=0,1, j=0,1)
b7
b0
Symbol
Address
G0MSK0, G0MSK1
00F416, 00F516
G1MSK0, G1MSK1
013416, 013516
Function
Masked data for received data
Set incomparable bit to "1"
After Reset
Indeterminate
Indeterminate
Setting Range RW
0016 to FF16
RW
Transmit CRC Code Register i (i=0,1)
b15
b8 b7
b0
Symbol
G0TCRC, G1TCRC
Address
00FB16-00FA16, 013B16-013A16
After Reset
000016
Function
RW
Result of the transmit CRC calculation^{(1, 2)}
RO
NOTES:
1. The calculated result is reset by setting the TE bit in the GiCR register to "0" (transmit disabled).
The CRCV bit in the GiEMR register selects a default value.
2. Transmit CRC calculation is performed with each bit of data transmitted while the TCRCE bit in
the GiETC register is set to "1" (used).
Receive CRC Code Register i (i=0,1)
b15
b8 b7
b0
Symbol
Address
G0RCRC, G1RCRC 00F916-00F816, 013916-013816
After Reset
Indeterminate
Function
RW
Result of the receive CRC calculation^{(1, 2, 3)}
RO
NOTES:
1. The calculated result is reset by setting the RCRCE bit in the GiERC register to "0" (not used).
If the ACRC bit in the GiEMR register is set to "1" (reset), the result is reset by matching data in the
GiCMPj register (j=0 to 3) with the received data.
2. The result is reset to the default value selected by the CRCV bit in the GiEMR register before
reception starts.
3. Receive CRC calculation is performed with every bit of data received while the RCRCE bit in the
GiERC register is set to "1" (used).
Figure 21.10 G0CMP0 to G0CMP3 Registers and G1CMP0 to G1CMP3 Registers
G0MSK0 and G0MSK1 Registers, G1MSK0 and G1MSK1 Registers
G0TCRC and G1TCRC Registers, G0RCRC and G1RCRC Registers
Rev. 1.00 Nov. 01, 2005 ^{Page 254} of 330
REJ09B0271-0100