M32C80 Datasheet, PDF (107/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
10. Interrupts
Table 10.2 Relocatable Vector Tables (Continued)
Interrupt Generated by
Vector Table Address
Address(L) to Address(H)⁽¹⁾
Software
Reference
Interrupt Number
Bus Conflict Detect, Start Condition Detect, +156 to +159 (009C16 to 009F16) 39
Stop Condition Detect (UART2)⁽³⁾,
Serial I/O
Bus Conflict Detect, Start Condition Detect, +160 to +163 (00A016 to 00A316) 40
Stop Condition Detect (UART3/UART0)⁽⁴⁾
Bus Conflict Detect, Start Condition Detect, +164 to +167 (00A416 to 00A716) 41
Stop Condition Detect (UART4/UART1)⁽⁴⁾
A/D0
+168 to +171 (00A816 to 00AB16) 42
A/D Converter
Key Input
+172 to +175 (00AC16 to 00AF16) 43
Interrupts
Intelligent I/O Interrupt 0
+176 to +179 (00B016 to 00B316) 44
Intelligent I/O
Intelligent I/O Interrupt 1
+180 to +183 (00B416 to 00B716) 45
Intelligent I/O Interrupt 2
+184 to +187 (00B816 to 00BB16) 46
Intelligent I/O Interrupt 3
+188 to +191 (00BC16 to 00BF16) 47
Intelligent I/O Interrupt 4
INT Instruction⁽²⁾
+192 to +195 (00C016 to 00C316) 48
+0 to +3 (000016 to 000316) to 0 to 63
Interrupts
+252 to +255 (00FC16 to 00FF16)
NOTES:
1. These addresses are relative to those in the INTB register.
2. The I flag does not disable interrupts.
3. In I²C mode, NACK, ACK or start/stop condition detection causes interrupts to be generated.
4. The IFSR6 bit in the IFSR register determines whether these addresses are used for an interrupt in UART0 or in
UART3.
The IFSR7 bit in the IFSR register determines whether these addresses are used for an interrupt in UART1 or in
UART4.
Rev. 1.00 Nov. 01, 2005 Page 88 of 330
REJ09B0271-0100