M32C80 Datasheet, PDF (225/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
16. Serial I/O (Special Function)
16.5 Special Mode 3 (GCI Mode)
In GCI mode, the external clock is synchronized with the transfer clock used in the clock synchronous serial
I/O mode.
Table 16.24 lists specifications of GCI mode. Table 16.25 lists registers settings. Tables 16.26 to 16.28 list
pin settings.
Table16.24 GCI Mode Specifications
Item
Specification
Transfer Data Format Transfer data : 8 bits long
Transfer Clock
The CKDIR bit in the UiMR register (i=0 to 4) is set to "1" (external clock selected):
input from the CLKi pin
________
Clock Synchronization Function Trigger signal input from the CTSi pin
Transmit/Receive Start To start data transmission and reception, meet the following conditions and then apply a
Condition
________
trigger signal to the CTSi pin:
- Set the TE bit in the UiC1 register to "1" (transmit enabled)
- Set the RE bit in the UiC1 register to "1" (receive enabled)
- Set the TI bit in the UiC1 register to "0" (Data in the UiTB register)
Interrupt Request
• While transmitting, the following condition can be selected:
Generation Timing
- The UiIRS bit in the UiC1 register is set to "0" (UiTB register empty):
when data is transferred from the UiTB register to the UARTi transmit register (transmission started)
- The UiIRS bit is set to "1" (Transmit completed):
when a data transmission from the UARTi transfer register is completed
• While receiving,
Error Detection
when data is transferred from the UARTi receive register to the UiRB register (reception
completed)
Overrun error⁽¹⁾
This error occurs when the seventh bit of the next received data is read before reading the
UiRB register.
NOTE:
1. If an overrun error occurs, the UiRB register is indeterminate. The IR bit setting in the SiRIC register does not
change to "1" (interrupt requested).
Rev. 1.00 Nov. 01, 2005 Page 206 of 330
REJ09B0271-0100