M32C80 Datasheet, PDF (159/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
14. Timer (Timer A)
Timer Ai Mode Register (i=0 to 4) (Event Counter Mode)
b7 b6 b5 b4 b3 b2 b1 b0
0
001
Symbol
Address
TA0MR to TA4MR 035616, 035716, 035816, 035916, 035A16
After Reset
0016
Bit
Symbol
Bit Name
Function
(When not processing
two-phase pulse signal)
Function
(When processing RW
two-phase pulse signal)
TMOD0
Operating Mode
b1b0
0 1: Event counter mode⁽¹⁾
RW
Select Bit
TMOD1
RW
Reserved Bit
Set to "0"
RW
(b2)
0: Counts falling edges
Count Polarity
MR1 _{Select Bit(2)}
of an external signal
1: Counts rising edges
Set to "0"
RW
of an external signal
Increment/Decrement ^{0: UDF registser}
MR2 Switching Source
setting
Set to "1"
RW
Select Bit
1: Input signal to
TAiOUT pin⁽³⁾
MR3 Set to "0" in event counter mode
RW
TCK0
Count Operation
Type Select Bit
0: Reloading
1: Free running
RW
TCK1
Two-Phase Pulse
Signal Processing Set to "0"
Operation Select Bit^(4,5)
0: Normal processing
operation
1: Multiply-by-4
RW
processing operation
NOTES:
1. The TAiTGH and TAiTGL bits in the ONSF or TRGSR register determine the count source in the event
counter mode.
2. MR1 bit setting is enabled only when counting how many times external signals are applied.
3. The timer decrements a counter value when an "L" signal is applied to the TAiOUT pin and the timer
increments a counter value when an "H" signal is applied to the TAiOUT pin.
4. The TCK1 bit is enabled only in the TA3MR register.
5. For two-phase pulse signal processing, set the TAjP bit in the UDF register (j=2 to 4) to "1" (two-
phase pulse signal processing function enabled). Also, set the TAjTGH and TAjTGL bits to "002"
(input to the TAjIN pin).
Figure 14.9 TA0MR to TA4MR Registers
Rev. 1.00 Nov. 01, 2005 Page 140 of 330
REJ09B0271-0100