M32C80 Datasheet, PDF (211/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
16. Serial I/O (Special Function)
Table 16.13 Register Settings in I²C Mode
Register
UiTB
UiRB
UiBRG
UiMR
UiC0
UiC1
UiSMR
UiSMR2
UiSMR3
UiSMR4
IFSR
i=0 to 4
Bit
Function
Master
Slave
7 to 0
Set transmit data
7 to 0
Received data can be read
8
ACK or NACK bit can be read
ABT
Arbitration lost detect flag
Disabled
OER
Overrun error flag
7 to 0
Set bit rate
Disabled
SMD2 to SMD0 Set to "0102"
CKDIR
Set to "0"
Set to "1"
IOPOL
Set to "0"
CLK1, CLK0
Select count source of the UiBRG register
Disabled
CRS
Disabled because the CRD bit is set to "1"
TXEPT
Transfer register empty flag
CRD, NCH
Set to "1"
CKPOL
Set to "0"
UFORM
Set to "1"
TE
Set to "1" to enable data transmission
TI
Transfer buffer empty flag
RE
Set to "1" to enable data reception
RI
Reception complete flag
UiRRM, UiLCH, Set to "0"
UiERE
IICM
Set to "1"
ABC
Select an arbitration lost detect timing
Disabled
BBS
Bus busy flag
7 to 3
Set to "000002"
IICM2
See Table 16.14
CSC
Set to "1" to enable clock synchronization
Set to "0"
SWC
Set to "1" to fix an "L" signal output from SCLi on the falling edge of the ninth bit
of the transfer clock
ALS
Set to "1" to terminate SDAi output when
Not used. Set to "0"
detecting the arbitration lost
STC
Not used. Set to "0"
Set to "1" to reset UARTi
by detecting the start condition
SWC2
Set to "1" for an "L" signal output from SCL forcibly
SDHI
Set to "1" to disable SDA output
SU1HIM
Set to "0"
SSE
Set to "0"
CKPH
See Table 16.14
DINC, NODC, ERR Set to "0"
DL2 to DL0
Set digital delay value for SDAi
STAREQ
Set to "1" when generating a start condition
Not used. Set to "0"
RSTAREQ
Set to "1" when generating a restart condition
STPREQ
Set to "1" when generating a stop condition
STSPSEL
Set to "1" when using a condition generating function
ACKD
ACKC
Select ACK or NACK
Set to "1" for ACK data output
SCLHI
Set to "1" to enable SCL output stop when
Not used. Set to "0"
detecting stop condition
SWC9
Not used. Set to "0"
IFSR6, IFSR7
Set to "1"
Set to "1" to fix an "L" signal output
from SCLi on the falling edge of the
ninth bit of the transfer clock
Rev. 1.00 Nov. 01, 2005 Page 192 of 330
REJ09B0271-0100