M32C80 Datasheet, PDF (139/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
13. DMACII
13. DMAC II
DMAC II performs memory-to-memory transfer, immediate data transfer and calculation transfer, which
transfers the sum of two data added by an interrupt request from any peripheral functions.
Table 13.1 lists specifications of DMAC II.
Table 13.1 DMAC II Specifications
Item
Specification
DMAC II Request Source Interrupt requests generated by all peripheral functions when the ILVL2 to
ILVL0 bits are set to "1112"
Transfer Data
• Data in memory is transferred to memory (memory-to-memory transfer)
• Immediate data is transferred to memory (immediate data transfer)
• Data in memory (or immediate data) + data in memory are transferred to
memory (calculation transfer)
Transfer Block
Transfer Space
8 bits or 16 bits
64-Kbyte space in addresses 0000016 to 0FFFF16(1, ²⁾
Transfer Direction
Fixed or forward address
Selected separately for each source address and destination address
Transfer Mode
Single transfer, burst transfer
Chained Transfer Function Parameters (transfer count, transfer address and other information) are
switched when transfer counter reaches zero
End-of-Transfer Interrupt Interrupt occurs when a transfer counter reaches zero
Multiple Transfer Function Multiple data can be transferred by a generated request for one DMAC II transfer
NOTES:
1. When transferring a 16-bit data to destination address 0FFFF16, it is transferred to 0FFFF16 and
1000016. The same transfer occurs when the source address is 0FFFF16.
2. The actual space where transfer can occurs is limited due to internal RAM capacity.
13.1 DMAC II Settings
DMAC II can be made available by setting up the following registers and tables.
• RLVL register
• DMAC II Index
• Interrupt control register of the peripheral function causing a DMAC II request
• The relocatable vector table of the peripheral function causing a DMAC II request
• IRLT bit in the IIOiIE register (i=0 to 4) to use the intelligent I/O
Refer to 10. Interrupts for details on the IIOiIE register.
13.1.1 RLVL Register
When the DMAII bit is set to "1" (DMAC II transfer) and the FSIT bit to "0" (normal interrupt), DMAC II is
activated by an interrupt request from any peripheral function with the ILVL2 to ILVL0 bits in the interrupt
control register set to "1112" (level 7).
Figure 13.1 shows the RLVL register.
Rev. 1.00 Nov. 01, 2005 Page 120 of 330
REJ09B0271-0100