M32C80 Datasheet, PDF (281/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
22. Programmable I/O Ports
22. Programmable I/O Ports
87 programmable I/O ports from ports P0 to P10 (excluding P85) are available. The direction registers
determine each port status, input or output. The pull-up control registers determine whether the ports,
divided into groups of four ports, are pulled up or not. P85 is an input port and no pull-up for this port is
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allowed. The P8_5 bit in the P8 register indicates an NMI input level since P85 shares pins with NMI.
Figures 22.1 to 22.4 show programmable I/O port configurations.
Each pin functions as the programmable I/O port, an I/O pin for internal peripheral functions or the bus
control pin.
To use the pins as input or output pins for internal peripheral functions, refer to the explanations for each
fuction. Refer to 7. Bus when used as the bus control pin.
The registers associated with the programmable I/O ports are as follows.
22.1 Port Pi Direction Register (PDi Register, i=0 to 10)
Figure 22.5 shows the PDi register.
The PDi register selects input or output status of a programmable I/O port. Each bit in the PDi register
corresponds to a port.
In memory expansion and microprocessor mode, the PDi register cannot control pins being used as bus
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control pins (A0 to A22, A23, D0 to D15, CS0 to CS3, WRL/WR, WRH/BHE, RD, BCLK/ALE/CLKOUT, HLDA/
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ALE, HOLD, ALE and RDY). No bit controlling P85 is provided in the direction registers.
22.2 Port Pi Register (Pi Register, i=0 to 10)
Figure 22.6 shows the Pi register.
The Pi register writes and reads data to communicate with external devices. The Pi register consists of a
port latch to hold output data and a circuit to read pin states. Each bit in the Pi register corresponds to a port.
In memory expansion and microprocessor mode, the Pi register cannot control pins being used as bus
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control pins (A0 to A22, A23, D0 to D15, CS0 to CS3, WRL/WR, WRH/BHE, RD, BCLK/ALE/CLKOUT, HLDA/
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ALE, HOLD, ALE and RDY).
22.3 Function Select Register Aj (PSj Register) (j=0 to 3)
Figures 22.7 and 22.8 show the PSj registers.
The PSj register selects either I/O port or peripheral function output if an I/O port shares pins with a periph-
eral function output (excluding DA0 and DA1.)
When multiple peripheral function outputs are assigned to a pin, set the PSL0 to PSL3, PSC, PSC3, and
PSD1 registers to select which function is used.
Tables 22.3 to 22.10 list peripheral function output control settings for each pin.
22.4 Function Select Register B0 to B3 (PSL0 to PSL3 Registers)
Figures 22.9 and 22.10 show the PSL0 to PSL3 registers.
When multiple peripheral function outputs are assigned to a pin, the PSL0 to PSL3 registers select which
peripheral function output is used.
Refer to 22.10 Analog Input and Other Peripheral Function Input for the PSL3_6 to PSL3_3 bits in the
PSL3 register.
Rev. 1.00 Nov. 01, 2005 ^{Page 262} of 330
REJ09B0271-0100